mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-04 11:26:54 +07:00
ARM: dts: r8a7792: sort subnodes of soc node
Sort the subnodes of the soc node to improve maintainability. The sort key is the address on the bus with instances of the same IP block grouped together. This patch should not introduce any functional change. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Simon Horman
parent
21b05c52ab
commit
3758e51b4b
@ -101,63 +101,6 @@ soc {
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#size-cells = <2>;
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ranges;
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apmu@e6152000 {
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compatible = "renesas,r8a7792-apmu", "renesas,apmu";
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reg = <0 0xe6152000 0 0x188>;
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cpus = <&cpu0 &cpu1>;
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0 0xf1001000 0 0x1000>,
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<0 0xf1002000 0 0x2000>,
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<0 0xf1004000 0 0x2000>,
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<0 0xf1006000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
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IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&cpg CPG_MOD 408>;
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clock-names = "clk";
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 408>;
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};
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irqc: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc-r8a7792", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 407>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 407>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a7792-rst";
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reg = <0 0xe6160000 0 0x0100>;
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};
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prr: chipid@ff000044 {
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compatible = "renesas,prr";
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reg = <0 0xff000044 0 4>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a7792-sysc";
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reg = <0 0xe6180000 0 0x0200>;
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#power-domain-cells = <1>;
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};
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a7792";
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reg = <0 0xe6060000 0 0x144>;
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};
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gpio0: gpio@e6050000 {
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compatible = "renesas,gpio-r8a7792",
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"renesas,rcar-gen2-gpio";
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@ -338,6 +281,155 @@ gpio11: gpio@e6055600 {
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resets = <&cpg 913>;
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};
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pfc: pin-controller@e6060000 {
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compatible = "renesas,pfc-r8a7792";
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reg = <0 0xe6060000 0 0x144>;
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};
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cpg: clock-controller@e6150000 {
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compatible = "renesas,r8a7792-cpg-mssr";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk>;
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clock-names = "extal";
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#clock-cells = <2>;
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#power-domain-cells = <0>;
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#reset-cells = <1>;
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};
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apmu@e6152000 {
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compatible = "renesas,r8a7792-apmu", "renesas,apmu";
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reg = <0 0xe6152000 0 0x188>;
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cpus = <&cpu0 &cpu1>;
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};
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rst: reset-controller@e6160000 {
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compatible = "renesas,r8a7792-rst";
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reg = <0 0xe6160000 0 0x0100>;
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};
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sysc: system-controller@e6180000 {
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compatible = "renesas,r8a7792-sysc";
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reg = <0 0xe6180000 0 0x0200>;
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#power-domain-cells = <1>;
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};
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irqc: interrupt-controller@e61c0000 {
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compatible = "renesas,irqc-r8a7792", "renesas,irqc";
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#interrupt-cells = <2>;
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interrupt-controller;
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reg = <0 0xe61c0000 0 0x200>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 407>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 407>;
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};
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icram0: sram@e63a0000 {
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compatible = "mmio-sram";
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reg = <0 0xe63a0000 0 0x12000>;
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};
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icram1: sram@e63c0000 {
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compatible = "mmio-sram";
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reg = <0 0xe63c0000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0xe63c0000 0x1000>;
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smp-sram@0 {
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compatible = "renesas,smp-sram";
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reg = <0 0x10>;
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};
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};
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/* I2C doesn't need pinmux */
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i2c0: i2c@e6508000 {
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compatible = "renesas,i2c-r8a7792",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6508000 0 0x40>;
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interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 931>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 931>;
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i2c-scl-internal-delay-ns = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@e6518000 {
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compatible = "renesas,i2c-r8a7792",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6518000 0 0x40>;
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interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 930>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 930>;
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i2c-scl-internal-delay-ns = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@e6530000 {
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compatible = "renesas,i2c-r8a7792",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6530000 0 0x40>;
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interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 929>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 929>;
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i2c-scl-internal-delay-ns = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@e6540000 {
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compatible = "renesas,i2c-r8a7792",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6540000 0 0x40>;
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interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 928>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 928>;
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i2c-scl-internal-delay-ns = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c4: i2c@e6520000 {
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compatible = "renesas,i2c-r8a7792",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6520000 0 0x40>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 927>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 927>;
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i2c-scl-internal-delay-ns = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c5: i2c@e6528000 {
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compatible = "renesas,i2c-r8a7792",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6528000 0 0x40>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 925>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 925>;
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i2c-scl-internal-delay-ns = <110>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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dmac0: dma-controller@e6700000 {
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compatible = "renesas,dmac-r8a7792",
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"renesas,rcar-dmac";
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@ -404,6 +496,35 @@ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
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dma-channels = <15>;
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};
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avb: ethernet@e6800000 {
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compatible = "renesas,etheravb-r8a7792",
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"renesas,etheravb-rcar-gen2";
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reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 812>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 812>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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qspi: spi@e6b10000 {
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compatible = "renesas,qspi-r8a7792", "renesas,qspi";
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reg = <0 0xe6b10000 0 0x2c>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 917>;
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dmas = <&dmac0 0x17>, <&dmac0 0x18>,
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<&dmac1 0x17>, <&dmac1 0x18>;
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dma-names = "tx", "rx", "tx", "rx";
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 917>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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scif0: serial@e6e60000 {
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compatible = "renesas,scif-r8a7792",
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"renesas,rcar-gen2-scif", "renesas,scif";
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@ -500,162 +621,6 @@ hscif1: serial@e62c8000 {
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status = "disabled";
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};
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icram0: sram@e63a0000 {
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compatible = "mmio-sram";
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reg = <0 0xe63a0000 0 0x12000>;
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};
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icram1: sram@e63c0000 {
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compatible = "mmio-sram";
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reg = <0 0xe63c0000 0 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0xe63c0000 0x1000>;
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smp-sram@0 {
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compatible = "renesas,smp-sram";
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reg = <0 0x10>;
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};
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};
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sdhi0: sd@ee100000 {
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compatible = "renesas,sdhi-r8a7792",
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"renesas,rcar-gen2-sdhi";
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reg = <0 0xee100000 0 0x328>;
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interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
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<&dmac1 0xcd>, <&dmac1 0xce>;
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dma-names = "tx", "rx", "tx", "rx";
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clocks = <&cpg CPG_MOD 314>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 314>;
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status = "disabled";
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};
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jpu: jpeg-codec@fe980000 {
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compatible = "renesas,jpu-r8a7792",
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"renesas,rcar-gen2-jpu";
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reg = <0 0xfe980000 0 0x10300>;
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interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 106>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 106>;
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};
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avb: ethernet@e6800000 {
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compatible = "renesas,etheravb-r8a7792",
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"renesas,etheravb-rcar-gen2";
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reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 812>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 812>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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/* I2C doesn't need pinmux */
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i2c0: i2c@e6508000 {
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compatible = "renesas,i2c-r8a7792",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6508000 0 0x40>;
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interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 931>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 931>;
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i2c-scl-internal-delay-ns = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c1: i2c@e6518000 {
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compatible = "renesas,i2c-r8a7792",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6518000 0 0x40>;
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interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 930>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 930>;
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i2c-scl-internal-delay-ns = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c2: i2c@e6530000 {
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compatible = "renesas,i2c-r8a7792",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6530000 0 0x40>;
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interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 929>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 929>;
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i2c-scl-internal-delay-ns = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c3: i2c@e6540000 {
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compatible = "renesas,i2c-r8a7792",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6540000 0 0x40>;
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interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 928>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 928>;
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i2c-scl-internal-delay-ns = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c4: i2c@e6520000 {
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compatible = "renesas,i2c-r8a7792",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6520000 0 0x40>;
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interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 927>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 927>;
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i2c-scl-internal-delay-ns = <6>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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i2c5: i2c@e6528000 {
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compatible = "renesas,i2c-r8a7792",
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"renesas,rcar-gen2-i2c";
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reg = <0 0xe6528000 0 0x40>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 925>;
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power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
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resets = <&cpg 925>;
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i2c-scl-internal-delay-ns = <110>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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qspi: spi@e6b10000 {
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compatible = "renesas,qspi-r8a7792", "renesas,qspi";
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reg = <0 0xe6b10000 0 0x2c>;
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interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 917>;
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dmas = <&dmac0 0x17>, <&dmac0 0x18>,
|
||||
<&dmac1 0x17>, <&dmac1 0x18>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 917>;
|
||||
num-cs = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
msiof0: spi@e6e20000 {
|
||||
compatible = "renesas,msiof-r8a7792",
|
||||
"renesas,rcar-gen2-msiof";
|
||||
@ -688,34 +653,6 @@ msiof1: spi@e6e10000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a7792";
|
||||
reg = <0 0xfeb00000 0 0x40000>;
|
||||
reg-names = "du";
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>;
|
||||
clock-names = "du.0", "du.1";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb0: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_rgb1: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
can0: can@e6e80000 {
|
||||
compatible = "renesas,can-r8a7792",
|
||||
"renesas,rcar-gen2-can";
|
||||
@ -808,6 +745,36 @@ vin5: video@e6ef5000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7792",
|
||||
"renesas,rcar-gen2-sdhi";
|
||||
reg = <0 0xee100000 0 0x328>;
|
||||
interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&dmac0 0xcd>, <&dmac0 0xce>,
|
||||
<&dmac1 0xcd>, <&dmac1 0xce>;
|
||||
dma-names = "tx", "rx", "tx", "rx";
|
||||
clocks = <&cpg CPG_MOD 314>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 314>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@f1001000 {
|
||||
compatible = "arm,gic-400";
|
||||
#interrupt-cells = <3>;
|
||||
interrupt-controller;
|
||||
reg = <0 0xf1001000 0 0x1000>,
|
||||
<0 0xf1002000 0 0x2000>,
|
||||
<0 0xf1004000 0 0x2000>,
|
||||
<0 0xf1006000 0 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
clocks = <&cpg CPG_MOD 408>;
|
||||
clock-names = "clk";
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 408>;
|
||||
};
|
||||
|
||||
vsp@fe928000 {
|
||||
compatible = "renesas,vsp1";
|
||||
reg = <0 0xfe928000 0 0x8000>;
|
||||
@ -835,14 +802,47 @@ vsp@fe938000 {
|
||||
resets = <&cpg 127>;
|
||||
};
|
||||
|
||||
cpg: clock-controller@e6150000 {
|
||||
compatible = "renesas,r8a7792-cpg-mssr";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>;
|
||||
clock-names = "extal";
|
||||
#clock-cells = <2>;
|
||||
#power-domain-cells = <0>;
|
||||
#reset-cells = <1>;
|
||||
jpu: jpeg-codec@fe980000 {
|
||||
compatible = "renesas,jpu-r8a7792",
|
||||
"renesas,rcar-gen2-jpu";
|
||||
reg = <0 0xfe980000 0 0x10300>;
|
||||
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 106>;
|
||||
power-domains = <&sysc R8A7792_PD_ALWAYS_ON>;
|
||||
resets = <&cpg 106>;
|
||||
};
|
||||
|
||||
du: display@feb00000 {
|
||||
compatible = "renesas,du-r8a7792";
|
||||
reg = <0 0xfeb00000 0 0x40000>;
|
||||
reg-names = "du";
|
||||
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&cpg CPG_MOD 724>,
|
||||
<&cpg CPG_MOD 723>;
|
||||
clock-names = "du.0", "du.1";
|
||||
status = "disabled";
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
du_out_rgb0: endpoint {
|
||||
};
|
||||
};
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
du_out_rgb1: endpoint {
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
prr: chipid@ff000044 {
|
||||
compatible = "renesas,prr";
|
||||
reg = <0 0xff000044 0 4>;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user