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media: camss: csiphy: Unify lane handling
Restructure lane configuration so it is simpler and will allow similar (although not the same) handling for different hardware versions. Signed-off-by: Todor Tomov <todor.tomov@linaro.org> Signed-off-by: Hans Verkuil <hansverk@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
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@ -86,7 +86,7 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
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{
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struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
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u8 settle_cnt;
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u8 val;
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u8 val, l = 0;
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int i = 0;
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settle_cnt = csiphy_settle_cnt_calc(pixel_clock, bpp, c->num_data,
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@ -104,34 +104,38 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
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val = cfg->combo_mode << 4;
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writel_relaxed(val, csiphy->base + CAMSS_CSI_PHY_GLBL_RESET);
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while (lane_mask) {
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if (lane_mask & 0x1) {
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writel_relaxed(0x10, csiphy->base +
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CAMSS_CSI_PHY_LNn_CFG2(i));
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writel_relaxed(settle_cnt, csiphy->base +
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CAMSS_CSI_PHY_LNn_CFG3(i));
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writel_relaxed(0x3f, csiphy->base +
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CAMSS_CSI_PHY_INTERRUPT_MASKn(i));
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writel_relaxed(0x3f, csiphy->base +
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CAMSS_CSI_PHY_INTERRUPT_CLEARn(i));
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}
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for (i = 0; i <= c->num_data; i++) {
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if (i == c->num_data)
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l = c->clk.pos;
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else
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l = c->data[i].pos;
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lane_mask >>= 1;
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i++;
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writel_relaxed(0x10, csiphy->base +
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CAMSS_CSI_PHY_LNn_CFG2(l));
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writel_relaxed(settle_cnt, csiphy->base +
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CAMSS_CSI_PHY_LNn_CFG3(l));
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writel_relaxed(0x3f, csiphy->base +
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CAMSS_CSI_PHY_INTERRUPT_MASKn(l));
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writel_relaxed(0x3f, csiphy->base +
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CAMSS_CSI_PHY_INTERRUPT_CLEARn(l));
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}
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}
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static void csiphy_lanes_disable(struct csiphy_device *csiphy, u8 lane_mask)
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static void csiphy_lanes_disable(struct csiphy_device *csiphy,
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struct csiphy_config *cfg)
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{
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struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
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u8 l = 0;
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int i = 0;
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while (lane_mask) {
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if (lane_mask & 0x1)
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writel_relaxed(0x0, csiphy->base +
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CAMSS_CSI_PHY_LNn_CFG2(i));
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for (i = 0; i <= c->num_data; i++) {
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if (i == c->num_data)
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l = c->clk.pos;
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else
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l = c->data[i].pos;
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lane_mask >>= 1;
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i++;
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writel_relaxed(0x0, csiphy->base +
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CAMSS_CSI_PHY_LNn_CFG2(l));
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}
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writel_relaxed(0x0, csiphy->base + CAMSS_CSI_PHY_GLBL_PWR_CFG);
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@ -296,9 +296,7 @@ static int csiphy_stream_on(struct csiphy_device *csiphy)
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*/
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static void csiphy_stream_off(struct csiphy_device *csiphy)
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{
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u8 lane_mask = csiphy_get_lane_mask(&csiphy->cfg.csi2->lane_cfg);
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csiphy->ops->lanes_disable(csiphy, lane_mask);
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csiphy->ops->lanes_disable(csiphy, &csiphy->cfg);
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}
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@ -51,7 +51,8 @@ struct csiphy_hw_ops {
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void (*lanes_enable)(struct csiphy_device *csiphy,
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struct csiphy_config *cfg,
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u32 pixel_clock, u8 bpp, u8 lane_mask);
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void (*lanes_disable)(struct csiphy_device *csiphy, u8 lane_mask);
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void (*lanes_disable)(struct csiphy_device *csiphy,
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struct csiphy_config *cfg);
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irqreturn_t (*isr)(int irq, void *dev);
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};
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