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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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drm/i915/selftests: Exercise resetting during non-user payloads
In selftests/live_hangcheck, we have a lot of tests for resetting simple spinners, but nothing quite prepared us for how the GPU reacted to triggering a reset outside of the safe spinner. These two subtests fill the ring with plain old empty, non-spinning requests, and then triggers a reset. Without a user-payload to blame, these requests will exercise the 'non-started' paths and mostly be replayed verbatim. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190226094922.31617-4-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
b300fde896
commit
368375107b
@ -415,6 +415,222 @@ static bool wait_for_idle(struct intel_engine_cs *engine)
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return wait_for(intel_engine_is_idle(engine), IGT_IDLE_TIMEOUT) == 0;
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}
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static int igt_reset_nop(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct intel_engine_cs *engine;
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struct i915_gem_context *ctx;
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unsigned int reset_count, count;
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enum intel_engine_id id;
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intel_wakeref_t wakeref;
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struct drm_file *file;
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IGT_TIMEOUT(end_time);
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int err = 0;
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/* Check that we can reset during non-user portions of requests */
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file = mock_file(i915);
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if (IS_ERR(file))
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return PTR_ERR(file);
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mutex_lock(&i915->drm.struct_mutex);
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ctx = live_context(i915, file);
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mutex_unlock(&i915->drm.struct_mutex);
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if (IS_ERR(ctx)) {
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err = PTR_ERR(ctx);
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goto out;
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}
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i915_gem_context_clear_bannable(ctx);
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wakeref = intel_runtime_pm_get(i915);
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reset_count = i915_reset_count(&i915->gpu_error);
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count = 0;
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do {
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mutex_lock(&i915->drm.struct_mutex);
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for_each_engine(engine, i915, id) {
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int i;
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for (i = 0; i < 16; i++) {
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struct i915_request *rq;
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rq = i915_request_alloc(engine, ctx);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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break;
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}
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i915_request_add(rq);
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}
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}
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mutex_unlock(&i915->drm.struct_mutex);
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igt_global_reset_lock(i915);
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i915_reset(i915, ALL_ENGINES, NULL);
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igt_global_reset_unlock(i915);
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if (i915_reset_failed(i915)) {
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err = -EIO;
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break;
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}
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if (i915_reset_count(&i915->gpu_error) !=
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reset_count + ++count) {
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pr_err("Full GPU reset not recorded!\n");
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err = -EINVAL;
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break;
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}
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if (!i915_reset_flush(i915)) {
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struct drm_printer p =
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drm_info_printer(i915->drm.dev);
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pr_err("%s failed to idle after reset\n",
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engine->name);
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intel_engine_dump(engine, &p,
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"%s\n", engine->name);
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err = -EIO;
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break;
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}
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err = igt_flush_test(i915, 0);
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if (err)
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break;
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} while (time_before(jiffies, end_time));
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pr_info("%s: %d resets\n", __func__, count);
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mutex_lock(&i915->drm.struct_mutex);
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err = igt_flush_test(i915, I915_WAIT_LOCKED);
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mutex_unlock(&i915->drm.struct_mutex);
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intel_runtime_pm_put(i915, wakeref);
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out:
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mock_file_free(i915, file);
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if (i915_reset_failed(i915))
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err = -EIO;
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return err;
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}
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static int igt_reset_nop_engine(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct intel_engine_cs *engine;
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struct i915_gem_context *ctx;
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enum intel_engine_id id;
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intel_wakeref_t wakeref;
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struct drm_file *file;
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int err = 0;
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/* Check that we can engine-reset during non-user portions */
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if (!intel_has_reset_engine(i915))
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return 0;
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file = mock_file(i915);
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if (IS_ERR(file))
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return PTR_ERR(file);
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mutex_lock(&i915->drm.struct_mutex);
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ctx = live_context(i915, file);
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mutex_unlock(&i915->drm.struct_mutex);
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if (IS_ERR(ctx)) {
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err = PTR_ERR(ctx);
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goto out;
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}
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i915_gem_context_clear_bannable(ctx);
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wakeref = intel_runtime_pm_get(i915);
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for_each_engine(engine, i915, id) {
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unsigned int reset_count, reset_engine_count;
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unsigned int count;
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IGT_TIMEOUT(end_time);
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reset_count = i915_reset_count(&i915->gpu_error);
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reset_engine_count = i915_reset_engine_count(&i915->gpu_error,
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engine);
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count = 0;
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set_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
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do {
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int i;
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if (!wait_for_idle(engine)) {
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pr_err("%s failed to idle before reset\n",
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engine->name);
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err = -EIO;
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break;
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}
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mutex_lock(&i915->drm.struct_mutex);
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for (i = 0; i < 16; i++) {
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struct i915_request *rq;
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rq = i915_request_alloc(engine, ctx);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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break;
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}
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i915_request_add(rq);
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}
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mutex_unlock(&i915->drm.struct_mutex);
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err = i915_reset_engine(engine, NULL);
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if (err) {
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pr_err("i915_reset_engine failed\n");
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break;
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}
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if (i915_reset_count(&i915->gpu_error) != reset_count) {
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pr_err("Full GPU reset recorded! (engine reset expected)\n");
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err = -EINVAL;
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break;
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}
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if (i915_reset_engine_count(&i915->gpu_error, engine) !=
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reset_engine_count + ++count) {
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pr_err("%s engine reset not recorded!\n",
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engine->name);
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err = -EINVAL;
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break;
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}
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if (!i915_reset_flush(i915)) {
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struct drm_printer p =
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drm_info_printer(i915->drm.dev);
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pr_err("%s failed to idle after reset\n",
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engine->name);
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intel_engine_dump(engine, &p,
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"%s\n", engine->name);
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err = -EIO;
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break;
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}
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} while (time_before(jiffies, end_time));
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clear_bit(I915_RESET_ENGINE + id, &i915->gpu_error.flags);
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pr_info("%s(%s): %d resets\n", __func__, engine->name, count);
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if (err)
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break;
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err = igt_flush_test(i915, 0);
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if (err)
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break;
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}
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mutex_lock(&i915->drm.struct_mutex);
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err = igt_flush_test(i915, I915_WAIT_LOCKED);
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mutex_unlock(&i915->drm.struct_mutex);
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intel_runtime_pm_put(i915, wakeref);
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out:
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mock_file_free(i915, file);
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if (i915_reset_failed(i915))
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err = -EIO;
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return err;
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}
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static int __igt_reset_engine(struct drm_i915_private *i915, bool active)
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{
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struct intel_engine_cs *engine;
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@ -1646,6 +1862,8 @@ int intel_hangcheck_live_selftests(struct drm_i915_private *i915)
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SUBTEST(igt_global_reset), /* attempt to recover GPU first */
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SUBTEST(igt_wedged_reset),
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SUBTEST(igt_hang_sanitycheck),
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SUBTEST(igt_reset_nop),
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SUBTEST(igt_reset_nop_engine),
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SUBTEST(igt_reset_idle_engine),
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SUBTEST(igt_reset_active_engine),
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SUBTEST(igt_reset_engines),
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