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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Merge remote-tracking branch 'asoc/fix/fsl-sai' into asoc-linus
This commit is contained in:
commit
3674b710a7
@ -327,7 +327,7 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
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{
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struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
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bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
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u32 tcsr, rcsr;
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u32 xcsr, count = 100;
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/*
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* The transmitter bit clock and frame sync are to be
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@ -338,9 +338,6 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
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regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
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FSL_SAI_CR2_SYNC);
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regmap_read(sai->regmap, FSL_SAI_TCSR, &tcsr);
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regmap_read(sai->regmap, FSL_SAI_RCSR, &rcsr);
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/*
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* It is recommended that the transmitter is the last enabled
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* and the first disabled.
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@ -349,17 +346,16 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (!(tcsr & FSL_SAI_CSR_FRDE || rcsr & FSL_SAI_CSR_FRDE)) {
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regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
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FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
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regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
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FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
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}
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regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
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FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
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regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
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FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
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regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
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FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
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regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
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FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
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regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
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FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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@ -370,14 +366,24 @@ static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
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FSL_SAI_CSR_xIE_MASK, 0);
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/* Check if the opposite FRDE is also disabled */
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if (!(tx ? rcsr & FSL_SAI_CSR_FRDE : tcsr & FSL_SAI_CSR_FRDE)) {
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regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
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if (!(xcsr & FSL_SAI_CSR_FRDE)) {
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/* Disable both directions and reset their FIFOs */
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regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
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FSL_SAI_CSR_TERE | FSL_SAI_CSR_FR,
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FSL_SAI_CSR_FR);
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FSL_SAI_CSR_TERE, 0);
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regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
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FSL_SAI_CSR_TERE | FSL_SAI_CSR_FR,
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FSL_SAI_CSR_FR);
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FSL_SAI_CSR_TERE, 0);
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/* TERE will remain set till the end of current frame */
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do {
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udelay(10);
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regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
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} while (--count && xcsr & FSL_SAI_CSR_TERE);
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regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
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FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
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regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
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FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
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}
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break;
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default:
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