mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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MIPS: unaligned: Surround load/store macros in do {} while statements
It's best to surround such complex macros with do {} while statements
so they can appear as independent logical blocks when used within other
control blocks.
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: <stable@vger.kernel.org> # v3.15+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9502/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Markos Chandras
Ralf Baechle
parent
eeb5389503
commit
3563c32d65
@ -110,6 +110,7 @@ extern void show_registers(struct pt_regs *regs);
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#ifdef __BIG_ENDIAN
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#define _LoadHW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ (".set\tnoat\n" \
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"1:\t"type##_lb("%0", "0(%2)")"\n" \
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"2:\t"type##_lbu("$1", "1(%2)")"\n\t"\
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@ -127,10 +128,12 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#ifndef CONFIG_CPU_MIPSR6
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#define _LoadW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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"1:\t"type##_lwl("%0", "(%2)")"\n" \
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"2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
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@ -146,10 +149,13 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#else
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/* MIPSR6 has no lwl instruction */
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#define _LoadW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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".set\tpush\n" \
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".set\tnoat\n\t" \
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@ -178,10 +184,13 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t4b, 11b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#endif /* CONFIG_CPU_MIPSR6 */
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#define _LoadHWU(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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".set\tnoat\n" \
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"1:\t"type##_lbu("%0", "0(%2)")"\n" \
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@ -201,10 +210,12 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#ifndef CONFIG_CPU_MIPSR6
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#define _LoadWU(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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"1:\t"type##_lwl("%0", "(%2)")"\n" \
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"2:\t"type##_lwr("%0", "3(%2)")"\n\t"\
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@ -222,9 +233,11 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#define _LoadDW(addr, value, res) \
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do { \
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__asm__ __volatile__ ( \
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"1:\tldl\t%0, (%2)\n" \
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"2:\tldr\t%0, 7(%2)\n\t" \
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@ -240,10 +253,13 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#else
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/* MIPSR6 has not lwl and ldl instructions */
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#define _LoadWU(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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".set\tpush\n\t" \
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".set\tnoat\n\t" \
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@ -272,9 +288,11 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t4b, 11b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#define _LoadDW(addr, value, res) \
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do { \
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__asm__ __volatile__ ( \
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".set\tpush\n\t" \
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".set\tnoat\n\t" \
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@ -319,11 +337,14 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t8b, 11b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#endif /* CONFIG_CPU_MIPSR6 */
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#define _StoreHW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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".set\tnoat\n" \
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"1:\t"type##_sb("%1", "1(%2)")"\n" \
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@ -342,10 +363,12 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=r" (res) \
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: "r" (value), "r" (addr), "i" (-EFAULT));
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: "r" (value), "r" (addr), "i" (-EFAULT));\
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} while(0)
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#ifndef CONFIG_CPU_MIPSR6
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#define _StoreW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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"1:\t"type##_swl("%1", "(%2)")"\n" \
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"2:\t"type##_swr("%1", "3(%2)")"\n\t"\
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@ -361,9 +384,11 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=r" (res) \
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: "r" (value), "r" (addr), "i" (-EFAULT));
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: "r" (value), "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#define _StoreDW(addr, value, res) \
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do { \
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__asm__ __volatile__ ( \
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"1:\tsdl\t%1,(%2)\n" \
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"2:\tsdr\t%1, 7(%2)\n\t" \
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@ -379,10 +404,13 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=r" (res) \
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: "r" (value), "r" (addr), "i" (-EFAULT));
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: "r" (value), "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#else
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/* MIPSR6 has no swl and sdl instructions */
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#define _StoreW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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".set\tpush\n\t" \
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".set\tnoat\n\t" \
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@ -409,9 +437,11 @@ extern void show_registers(struct pt_regs *regs);
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".previous" \
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: "=&r" (res) \
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: "r" (value), "r" (addr), "i" (-EFAULT) \
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: "memory");
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: "memory"); \
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} while(0)
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#define StoreDW(addr, value, res) \
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do { \
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__asm__ __volatile__ ( \
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".set\tpush\n\t" \
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".set\tnoat\n\t" \
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@ -451,12 +481,15 @@ extern void show_registers(struct pt_regs *regs);
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".previous" \
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: "=&r" (res) \
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: "r" (value), "r" (addr), "i" (-EFAULT) \
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: "memory");
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: "memory"); \
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} while(0)
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#endif /* CONFIG_CPU_MIPSR6 */
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#else /* __BIG_ENDIAN */
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#define _LoadHW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ (".set\tnoat\n" \
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"1:\t"type##_lb("%0", "1(%2)")"\n" \
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"2:\t"type##_lbu("$1", "0(%2)")"\n\t"\
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@ -474,10 +507,12 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#ifndef CONFIG_CPU_MIPSR6
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#define _LoadW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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"1:\t"type##_lwl("%0", "3(%2)")"\n" \
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"2:\t"type##_lwr("%0", "(%2)")"\n\t"\
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@ -493,10 +528,13 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#else
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/* MIPSR6 has no lwl instruction */
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#define _LoadW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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".set\tpush\n" \
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".set\tnoat\n\t" \
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@ -525,11 +563,14 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t4b, 11b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#endif /* CONFIG_CPU_MIPSR6 */
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#define _LoadHWU(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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".set\tnoat\n" \
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"1:\t"type##_lbu("%0", "1(%2)")"\n" \
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@ -549,10 +590,12 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#ifndef CONFIG_CPU_MIPSR6
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#define _LoadWU(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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"1:\t"type##_lwl("%0", "3(%2)")"\n" \
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"2:\t"type##_lwr("%0", "(%2)")"\n\t"\
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@ -570,9 +613,11 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#define _LoadDW(addr, value, res) \
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do { \
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__asm__ __volatile__ ( \
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"1:\tldl\t%0, 7(%2)\n" \
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"2:\tldr\t%0, (%2)\n\t" \
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@ -588,10 +633,13 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#else
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/* MIPSR6 has not lwl and ldl instructions */
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#define _LoadWU(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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".set\tpush\n\t" \
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".set\tnoat\n\t" \
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@ -620,9 +668,11 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t4b, 11b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#define _LoadDW(addr, value, res) \
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do { \
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__asm__ __volatile__ ( \
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".set\tpush\n\t" \
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".set\tnoat\n\t" \
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@ -667,10 +717,12 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t8b, 11b\n\t" \
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".previous" \
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: "=&r" (value), "=r" (res) \
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: "r" (addr), "i" (-EFAULT));
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: "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#endif /* CONFIG_CPU_MIPSR6 */
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#define _StoreHW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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".set\tnoat\n" \
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"1:\t"type##_sb("%1", "0(%2)")"\n" \
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@ -689,9 +741,12 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=r" (res) \
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: "r" (value), "r" (addr), "i" (-EFAULT));
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: "r" (value), "r" (addr), "i" (-EFAULT));\
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} while(0)
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#ifndef CONFIG_CPU_MIPSR6
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#define _StoreW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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"1:\t"type##_swl("%1", "3(%2)")"\n" \
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"2:\t"type##_swr("%1", "(%2)")"\n\t"\
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@ -707,9 +762,11 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=r" (res) \
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: "r" (value), "r" (addr), "i" (-EFAULT));
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: "r" (value), "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#define _StoreDW(addr, value, res) \
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do { \
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__asm__ __volatile__ ( \
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"1:\tsdl\t%1, 7(%2)\n" \
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"2:\tsdr\t%1, (%2)\n\t" \
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@ -725,10 +782,13 @@ extern void show_registers(struct pt_regs *regs);
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STR(PTR)"\t2b, 4b\n\t" \
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".previous" \
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: "=r" (res) \
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: "r" (value), "r" (addr), "i" (-EFAULT));
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: "r" (value), "r" (addr), "i" (-EFAULT)); \
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} while(0)
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#else
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/* MIPSR6 has no swl and sdl instructions */
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#define _StoreW(addr, value, res, type) \
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do { \
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__asm__ __volatile__ ( \
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".set\tpush\n\t" \
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".set\tnoat\n\t" \
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@ -755,9 +815,11 @@ extern void show_registers(struct pt_regs *regs);
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".previous" \
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: "=&r" (res) \
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: "r" (value), "r" (addr), "i" (-EFAULT) \
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: "memory");
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: "memory"); \
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} while(0)
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#define _StoreDW(addr, value, res) \
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do { \
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__asm__ __volatile__ ( \
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".set\tpush\n\t" \
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".set\tnoat\n\t" \
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@ -797,7 +859,9 @@ extern void show_registers(struct pt_regs *regs);
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".previous" \
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: "=&r" (res) \
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: "r" (value), "r" (addr), "i" (-EFAULT) \
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: "memory");
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: "memory"); \
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} while(0)
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#endif /* CONFIG_CPU_MIPSR6 */
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#endif
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