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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 19:43:54 +07:00
drm/i915/selftests: Check that whitelisted registers are accessible
There is no point in whitelisting a register that the user then cannot write to, so check the register exists before merging such patches. v2: Mark SLICE_COMMON_ECO_CHICKEN1 [731c] as write-only v3: Use different variables for different meanings! Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Dale B Stimson <dale.b.stimson@intel.com> Cc: Michał Winiarski <michal.winiarski@intel.com> Reviewed-by: Michał Winiarski <michal.winiarski@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190301140404.26690-6-chris@chris-wilson.co.uk Link: https://patchwork.freedesktop.org/patch/msgid/20190301160108.19039-1-chris@chris-wilson.co.uk
This commit is contained in:
Chris Wilson
parent
c384afe352
commit
34ae8455f4
@ -12,6 +12,14 @@
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#include "igt_spinner.h"
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#include "igt_wedge_me.h"
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#include "mock_context.h"
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#include "mock_drm.h"
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static const struct wo_register {
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enum intel_platform platform;
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u32 reg;
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} wo_registers[] = {
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{ INTEL_GEMINILAKE, 0x731c }
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};
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#define REF_NAME_MAX (INTEL_ENGINE_CS_MAX_NAME + 4)
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struct wa_lists {
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@ -74,7 +82,7 @@ read_nonprivs(struct i915_gem_context *ctx, struct intel_engine_cs *engine)
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if (IS_ERR(result))
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return result;
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i915_gem_object_set_cache_level(result, I915_CACHE_LLC);
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i915_gem_object_set_cache_coherency(result, I915_CACHE_LLC);
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cs = i915_gem_object_pin_map(result, I915_MAP_WB);
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if (IS_ERR(cs)) {
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@ -331,6 +339,373 @@ static int check_whitelist_across_reset(struct intel_engine_cs *engine,
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return err;
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}
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static struct i915_vma *create_scratch(struct i915_gem_context *ctx)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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void *ptr;
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int err;
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obj = i915_gem_object_create_internal(ctx->i915, PAGE_SIZE);
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if (IS_ERR(obj))
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return ERR_CAST(obj);
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i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
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ptr = i915_gem_object_pin_map(obj, I915_MAP_WB);
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if (IS_ERR(ptr)) {
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err = PTR_ERR(ptr);
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goto err_obj;
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}
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memset(ptr, 0xc5, PAGE_SIZE);
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i915_gem_object_unpin_map(obj);
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vma = i915_vma_instance(obj, &ctx->ppgtt->vm, NULL);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto err_obj;
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}
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err = i915_vma_pin(vma, 0, 0, PIN_USER);
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if (err)
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goto err_obj;
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err = i915_gem_object_set_to_cpu_domain(obj, false);
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if (err)
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goto err_obj;
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return vma;
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err_obj:
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i915_gem_object_put(obj);
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return ERR_PTR(err);
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}
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static struct i915_vma *create_batch(struct i915_gem_context *ctx)
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{
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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int err;
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obj = i915_gem_object_create_internal(ctx->i915, 16 * PAGE_SIZE);
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if (IS_ERR(obj))
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return ERR_CAST(obj);
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vma = i915_vma_instance(obj, &ctx->ppgtt->vm, NULL);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto err_obj;
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}
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err = i915_vma_pin(vma, 0, 0, PIN_USER);
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if (err)
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goto err_obj;
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err = i915_gem_object_set_to_wc_domain(obj, true);
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if (err)
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goto err_obj;
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return vma;
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err_obj:
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i915_gem_object_put(obj);
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return ERR_PTR(err);
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}
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static u32 reg_write(u32 old, u32 new, u32 rsvd)
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{
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if (rsvd == 0x0000ffff) {
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old &= ~(new >> 16);
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old |= new & (new >> 16);
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} else {
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old &= ~rsvd;
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old |= new & rsvd;
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}
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return old;
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}
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static bool wo_register(struct intel_engine_cs *engine, u32 reg)
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{
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enum intel_platform platform = INTEL_INFO(engine->i915)->platform;
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int i;
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for (i = 0; i < ARRAY_SIZE(wo_registers); i++) {
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if (wo_registers[i].platform == platform &&
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wo_registers[i].reg == reg)
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return true;
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}
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return false;
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}
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static int check_dirty_whitelist(struct i915_gem_context *ctx,
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struct intel_engine_cs *engine)
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{
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const u32 values[] = {
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0x00000000,
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0x01010101,
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0x10100101,
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0x03030303,
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0x30300303,
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0x05050505,
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0x50500505,
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0x0f0f0f0f,
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0xf00ff00f,
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0x10101010,
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0xf0f01010,
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0x30303030,
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0xa0a03030,
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0x50505050,
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0xc0c05050,
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0xf0f0f0f0,
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0x11111111,
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0x33333333,
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0x55555555,
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0x0000ffff,
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0x00ff00ff,
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0xff0000ff,
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0xffff00ff,
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0xffffffff,
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};
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struct i915_vma *scratch;
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struct i915_vma *batch;
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int err = 0, i, v;
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u32 *cs, *results;
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scratch = create_scratch(ctx);
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if (IS_ERR(scratch))
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return PTR_ERR(scratch);
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batch = create_batch(ctx);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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goto out_scratch;
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}
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for (i = 0; i < engine->whitelist.count; i++) {
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u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg);
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u64 addr = scratch->node.start;
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struct i915_request *rq;
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u32 srm, lrm, rsvd;
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u32 expect;
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int idx;
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if (wo_register(engine, reg))
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continue;
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srm = MI_STORE_REGISTER_MEM;
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lrm = MI_LOAD_REGISTER_MEM;
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if (INTEL_GEN(ctx->i915) >= 8)
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lrm++, srm++;
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pr_debug("%s: Writing garbage to %x\n",
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engine->name, reg);
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cs = i915_gem_object_pin_map(batch->obj, I915_MAP_WC);
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if (IS_ERR(cs)) {
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err = PTR_ERR(cs);
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goto out_batch;
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}
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/* SRM original */
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*cs++ = srm;
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*cs++ = reg;
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*cs++ = lower_32_bits(addr);
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*cs++ = upper_32_bits(addr);
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idx = 1;
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for (v = 0; v < ARRAY_SIZE(values); v++) {
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/* LRI garbage */
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*cs++ = MI_LOAD_REGISTER_IMM(1);
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*cs++ = reg;
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*cs++ = values[v];
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/* SRM result */
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*cs++ = srm;
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*cs++ = reg;
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*cs++ = lower_32_bits(addr + sizeof(u32) * idx);
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*cs++ = upper_32_bits(addr + sizeof(u32) * idx);
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idx++;
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}
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for (v = 0; v < ARRAY_SIZE(values); v++) {
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/* LRI garbage */
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*cs++ = MI_LOAD_REGISTER_IMM(1);
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*cs++ = reg;
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*cs++ = ~values[v];
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/* SRM result */
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*cs++ = srm;
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*cs++ = reg;
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*cs++ = lower_32_bits(addr + sizeof(u32) * idx);
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*cs++ = upper_32_bits(addr + sizeof(u32) * idx);
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idx++;
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}
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GEM_BUG_ON(idx * sizeof(u32) > scratch->size);
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/* LRM original -- don't leave garbage in the context! */
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*cs++ = lrm;
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*cs++ = reg;
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*cs++ = lower_32_bits(addr);
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*cs++ = upper_32_bits(addr);
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*cs++ = MI_BATCH_BUFFER_END;
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i915_gem_object_unpin_map(batch->obj);
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i915_gem_chipset_flush(ctx->i915);
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rq = i915_request_alloc(engine, ctx);
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if (IS_ERR(rq)) {
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err = PTR_ERR(rq);
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goto out_batch;
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}
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if (engine->emit_init_breadcrumb) { /* Be nice if we hang */
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err = engine->emit_init_breadcrumb(rq);
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if (err)
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goto err_request;
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}
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err = engine->emit_bb_start(rq,
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batch->node.start, PAGE_SIZE,
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0);
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if (err)
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goto err_request;
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err_request:
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i915_request_add(rq);
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if (err)
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goto out_batch;
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if (i915_request_wait(rq, I915_WAIT_LOCKED, HZ / 5) < 0) {
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pr_err("%s: Futzing %x timedout; cancelling test\n",
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engine->name, reg);
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i915_gem_set_wedged(ctx->i915);
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err = -EIO;
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goto out_batch;
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}
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results = i915_gem_object_pin_map(scratch->obj, I915_MAP_WB);
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if (IS_ERR(results)) {
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err = PTR_ERR(results);
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goto out_batch;
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}
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GEM_BUG_ON(values[ARRAY_SIZE(values) - 1] != 0xffffffff);
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rsvd = results[ARRAY_SIZE(values)]; /* detect write masking */
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if (!rsvd) {
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pr_err("%s: Unable to write to whitelisted register %x\n",
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engine->name, reg);
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err = -EINVAL;
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goto out_unpin;
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}
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expect = results[0];
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idx = 1;
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for (v = 0; v < ARRAY_SIZE(values); v++) {
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expect = reg_write(expect, values[v], rsvd);
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if (results[idx] != expect)
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err++;
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idx++;
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}
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for (v = 0; v < ARRAY_SIZE(values); v++) {
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expect = reg_write(expect, ~values[v], rsvd);
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if (results[idx] != expect)
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err++;
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idx++;
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}
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if (err) {
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pr_err("%s: %d mismatch between values written to whitelisted register [%x], and values read back!\n",
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engine->name, err, reg);
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pr_info("%s: Whitelisted register: %x, original value %08x, rsvd %08x\n",
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engine->name, reg, results[0], rsvd);
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expect = results[0];
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idx = 1;
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for (v = 0; v < ARRAY_SIZE(values); v++) {
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u32 w = values[v];
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expect = reg_write(expect, w, rsvd);
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pr_info("Wrote %08x, read %08x, expect %08x\n",
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w, results[idx], expect);
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idx++;
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}
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for (v = 0; v < ARRAY_SIZE(values); v++) {
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u32 w = ~values[v];
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expect = reg_write(expect, w, rsvd);
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pr_info("Wrote %08x, read %08x, expect %08x\n",
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w, results[idx], expect);
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idx++;
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}
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err = -EINVAL;
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}
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out_unpin:
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i915_gem_object_unpin_map(scratch->obj);
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if (err)
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break;
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}
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if (igt_flush_test(ctx->i915, I915_WAIT_LOCKED))
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err = -EIO;
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out_batch:
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i915_vma_unpin_and_release(&batch, 0);
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out_scratch:
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i915_vma_unpin_and_release(&scratch, 0);
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return err;
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}
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static int live_dirty_whitelist(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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struct intel_engine_cs *engine;
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struct i915_gem_context *ctx;
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enum intel_engine_id id;
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intel_wakeref_t wakeref;
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struct drm_file *file;
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int err = 0;
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/* Can the user write to the whitelisted registers? */
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if (INTEL_GEN(i915) < 7) /* minimum requirement for LRI, SRM, LRM */
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return 0;
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wakeref = intel_runtime_pm_get(i915);
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mutex_unlock(&i915->drm.struct_mutex);
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file = mock_file(i915);
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mutex_lock(&i915->drm.struct_mutex);
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if (IS_ERR(file)) {
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err = PTR_ERR(file);
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goto out_rpm;
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}
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ctx = live_context(i915, file);
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if (IS_ERR(ctx)) {
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err = PTR_ERR(ctx);
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goto out_file;
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}
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for_each_engine(engine, i915, id) {
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if (engine->whitelist.count == 0)
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continue;
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err = check_dirty_whitelist(ctx, engine);
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if (err)
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goto out_file;
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}
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out_file:
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mutex_unlock(&i915->drm.struct_mutex);
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mock_file_free(i915, file);
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mutex_lock(&i915->drm.struct_mutex);
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out_rpm:
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intel_runtime_pm_put(i915, wakeref);
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return err;
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}
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static int live_reset_whitelist(void *arg)
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{
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struct drm_i915_private *i915 = arg;
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@ -504,6 +879,7 @@ live_engine_reset_gt_engine_workarounds(void *arg)
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int intel_workarounds_live_selftests(struct drm_i915_private *i915)
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{
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static const struct i915_subtest tests[] = {
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SUBTEST(live_dirty_whitelist),
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SUBTEST(live_reset_whitelist),
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SUBTEST(live_gpu_reset_gt_engine_workarounds),
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SUBTEST(live_engine_reset_gt_engine_workarounds),
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