mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 16:23:29 +07:00
wil6210: prevent deep sleep of 60G device in critical paths
In idle times 60G device can enter deep sleep and turn off its XTAL clock. Host access triggers the device power-up flow which will hold the AHB during XTAL stabilization until device switches from slow-clock to XTAL clock. This behavior can stall the PCIe bus for some arbitrary period of time. In order to prevent this stall, host can vote for High Latency Access Policy (HALP) before reading from PCIe bus. This vote will wakeup the device from deep sleep and prevent deep sleep until unvote is done. Signed-off-by: Maya Erez <qca_merez@qca.qualcomm.com> Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
This commit is contained in:
Maya Erez
Kalle Valo
parent
54eaa8c69e
commit
349214c1e7
@ -171,6 +171,8 @@ static void wil_print_ring(struct seq_file *s, const char *prefix,
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int rsize;
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uint i;
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wil_halp_vote(wil);
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wil_memcpy_fromio_32(&r, off, sizeof(r));
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wil_mbox_ring_le2cpus(&r);
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/*
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@ -236,6 +238,7 @@ static void wil_print_ring(struct seq_file *s, const char *prefix,
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}
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out:
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seq_puts(s, "}\n");
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wil_halp_unvote(wil);
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}
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static int wil_mbox_debugfs_show(struct seq_file *s, void *data)
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@ -500,9 +503,9 @@ static ssize_t wil_read_file_ioblob(struct file *file, char __user *user_buf,
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size_t count, loff_t *ppos)
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{
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enum { max_count = 4096 };
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struct debugfs_blob_wrapper *blob = file->private_data;
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struct wil_blob_wrapper *wil_blob = file->private_data;
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loff_t pos = *ppos;
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size_t available = blob->size;
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size_t available = wil_blob->blob.size;
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void *buf;
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size_t ret;
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@ -521,8 +524,9 @@ static ssize_t wil_read_file_ioblob(struct file *file, char __user *user_buf,
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if (!buf)
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return -ENOMEM;
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wil_memcpy_fromio_32(buf, (const volatile void __iomem *)blob->data +
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pos, count);
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wil_memcpy_fromio_halp_vote(wil_blob->wil, buf,
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(const volatile void __iomem *)
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wil_blob->blob.data + pos, count);
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ret = copy_to_user(user_buf, buf, count);
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kfree(buf);
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@ -545,9 +549,9 @@ static
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struct dentry *wil_debugfs_create_ioblob(const char *name,
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umode_t mode,
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struct dentry *parent,
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struct debugfs_blob_wrapper *blob)
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struct wil_blob_wrapper *wil_blob)
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{
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return debugfs_create_file(name, mode, parent, blob, &fops_ioblob);
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return debugfs_create_file(name, mode, parent, wil_blob, &fops_ioblob);
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}
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/*---reset---*/
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@ -1445,16 +1449,18 @@ static void wil6210_debugfs_init_blobs(struct wil6210_priv *wil,
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char name[32];
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for (i = 0; i < ARRAY_SIZE(fw_mapping); i++) {
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struct debugfs_blob_wrapper *blob = &wil->blobs[i];
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struct wil_blob_wrapper *wil_blob = &wil->blobs[i];
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struct debugfs_blob_wrapper *blob = &wil_blob->blob;
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const struct fw_map *map = &fw_mapping[i];
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if (!map->name)
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continue;
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wil_blob->wil = wil;
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blob->data = (void * __force)wil->csr + HOSTADDR(map->host);
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blob->size = map->to - map->from;
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snprintf(name, sizeof(name), "blob_%s", map->name);
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wil_debugfs_create_ioblob(name, S_IRUGO, dbg, blob);
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wil_debugfs_create_ioblob(name, S_IRUGO, dbg, wil_blob);
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}
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}
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@ -35,17 +35,19 @@
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*
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*/
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#define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
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#define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
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#define WIL6210_IRQ_DISABLE_NO_HALP (0xF7FFFFFFUL)
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#define WIL6210_IMC_RX (BIT_DMA_EP_RX_ICR_RX_DONE | \
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BIT_DMA_EP_RX_ICR_RX_HTRSH)
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#define WIL6210_IMC_RX_NO_RX_HTRSH (WIL6210_IMC_RX & \
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(~(BIT_DMA_EP_RX_ICR_RX_HTRSH)))
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#define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \
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BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
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#define WIL6210_IMC_MISC (ISR_MISC_FW_READY | \
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ISR_MISC_MBOX_EVT | \
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ISR_MISC_FW_ERROR)
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#define WIL6210_IMC_MISC_NO_HALP (ISR_MISC_FW_READY | \
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ISR_MISC_MBOX_EVT | \
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ISR_MISC_FW_ERROR)
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#define WIL6210_IMC_MISC (WIL6210_IMC_MISC_NO_HALP | \
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BIT_DMA_EP_MISC_ICR_HALP)
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#define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
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BIT_DMA_PSEUDO_CAUSE_TX | \
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BIT_DMA_PSEUDO_CAUSE_MISC))
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@ -53,6 +55,7 @@
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#if defined(CONFIG_WIL6210_ISR_COR)
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/* configure to Clear-On-Read mode */
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#define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL)
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#define WIL_ICR_ICC_MISC_VALUE (0xF7FFFFFFUL)
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static inline void wil_icr_clear(u32 x, void __iomem *addr)
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{
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@ -60,6 +63,7 @@ static inline void wil_icr_clear(u32 x, void __iomem *addr)
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#else /* defined(CONFIG_WIL6210_ISR_COR) */
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/* configure to Write-1-to-Clear mode */
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#define WIL_ICR_ICC_VALUE (0UL)
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#define WIL_ICR_ICC_MISC_VALUE (0UL)
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static inline void wil_icr_clear(u32 x, void __iomem *addr)
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{
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@ -88,10 +92,21 @@ static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
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WIL6210_IRQ_DISABLE);
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}
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static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
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static void wil6210_mask_irq_misc(struct wil6210_priv *wil, bool mask_halp)
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{
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wil_dbg_irq(wil, "%s: mask_halp(%s)\n", __func__,
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mask_halp ? "true" : "false");
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wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
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WIL6210_IRQ_DISABLE);
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mask_halp ? WIL6210_IRQ_DISABLE : WIL6210_IRQ_DISABLE_NO_HALP);
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}
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static void wil6210_mask_halp(struct wil6210_priv *wil)
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{
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wil_dbg_irq(wil, "%s()\n", __func__);
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wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMS),
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BIT_DMA_EP_MISC_ICR_HALP);
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}
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static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
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@ -117,10 +132,21 @@ void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
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unmask_rx_htrsh ? WIL6210_IMC_RX : WIL6210_IMC_RX_NO_RX_HTRSH);
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}
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static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
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static void wil6210_unmask_irq_misc(struct wil6210_priv *wil, bool unmask_halp)
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{
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wil_dbg_irq(wil, "%s: unmask_halp(%s)\n", __func__,
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unmask_halp ? "true" : "false");
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wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
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WIL6210_IMC_MISC);
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unmask_halp ? WIL6210_IMC_MISC : WIL6210_IMC_MISC_NO_HALP);
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}
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static void wil6210_unmask_halp(struct wil6210_priv *wil)
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{
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wil_dbg_irq(wil, "%s()\n", __func__);
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wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, IMC),
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BIT_DMA_EP_MISC_ICR_HALP);
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}
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static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
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@ -138,7 +164,7 @@ void wil_mask_irq(struct wil6210_priv *wil)
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wil6210_mask_irq_tx(wil);
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wil6210_mask_irq_rx(wil);
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wil6210_mask_irq_misc(wil);
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wil6210_mask_irq_misc(wil, true);
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wil6210_mask_irq_pseudo(wil);
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}
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@ -151,12 +177,12 @@ void wil_unmask_irq(struct wil6210_priv *wil)
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wil_w(wil, RGF_DMA_EP_TX_ICR + offsetof(struct RGF_ICR, ICC),
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WIL_ICR_ICC_VALUE);
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wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICC),
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WIL_ICR_ICC_VALUE);
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WIL_ICR_ICC_MISC_VALUE);
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wil6210_unmask_irq_pseudo(wil);
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wil6210_unmask_irq_tx(wil);
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wil6210_unmask_irq_rx(wil);
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wil6210_unmask_irq_misc(wil);
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wil6210_unmask_irq_misc(wil, true);
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}
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void wil_configure_interrupt_moderation(struct wil6210_priv *wil)
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@ -345,7 +371,7 @@ static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
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return IRQ_NONE;
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}
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wil6210_mask_irq_misc(wil);
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wil6210_mask_irq_misc(wil, false);
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if (isr & ISR_MISC_FW_ERROR) {
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u32 fw_assert_code = wil_r(wil, RGF_FW_ASSERT_CODE);
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@ -373,12 +399,19 @@ static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
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isr &= ~ISR_MISC_FW_READY;
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}
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if (isr & BIT_DMA_EP_MISC_ICR_HALP) {
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wil_dbg_irq(wil, "%s: HALP IRQ invoked\n", __func__);
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wil6210_mask_halp(wil);
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isr &= ~BIT_DMA_EP_MISC_ICR_HALP;
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complete(&wil->halp.comp);
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}
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wil->isr_misc = isr;
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if (isr) {
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return IRQ_WAKE_THREAD;
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} else {
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wil6210_unmask_irq_misc(wil);
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wil6210_unmask_irq_misc(wil, false);
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return IRQ_HANDLED;
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}
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}
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@ -415,7 +448,7 @@ static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
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wil->isr_misc = 0;
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wil6210_unmask_irq_misc(wil);
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wil6210_unmask_irq_misc(wil, false);
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return IRQ_HANDLED;
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}
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@ -557,6 +590,23 @@ void wil6210_clear_irq(struct wil6210_priv *wil)
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wmb(); /* make sure write completed */
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}
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void wil6210_set_halp(struct wil6210_priv *wil)
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{
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wil_dbg_misc(wil, "%s()\n", __func__);
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wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICS),
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BIT_DMA_EP_MISC_ICR_HALP);
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}
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void wil6210_clear_halp(struct wil6210_priv *wil)
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{
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wil_dbg_misc(wil, "%s()\n", __func__);
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wil_w(wil, RGF_DMA_EP_MISC_ICR + offsetof(struct RGF_ICR, ICR),
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BIT_DMA_EP_MISC_ICR_HALP);
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wil6210_unmask_halp(wil);
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}
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int wil6210_init_irq(struct wil6210_priv *wil, int irq, bool use_msi)
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{
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int rc;
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@ -23,6 +23,8 @@
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#include "wmi.h"
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#include "boot_loader.h"
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#define WAIT_FOR_HALP_VOTE_MS 100
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bool debug_fw; /* = false; */
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module_param(debug_fw, bool, S_IRUGO);
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MODULE_PARM_DESC(debug_fw, " do not perform card reset. For FW debug");
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@ -132,6 +134,14 @@ void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src,
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*d++ = __raw_readl(s++);
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}
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void wil_memcpy_fromio_halp_vote(struct wil6210_priv *wil, void *dst,
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const volatile void __iomem *src, size_t count)
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{
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wil_halp_vote(wil);
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wil_memcpy_fromio_32(dst, src, count);
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wil_halp_unvote(wil);
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}
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void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
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size_t count)
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{
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@ -142,6 +152,15 @@ void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
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__raw_writel(*s++, d++);
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}
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void wil_memcpy_toio_halp_vote(struct wil6210_priv *wil,
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volatile void __iomem *dst,
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const void *src, size_t count)
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{
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wil_halp_vote(wil);
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wil_memcpy_toio_32(dst, src, count);
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wil_halp_unvote(wil);
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}
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static void wil_disconnect_cid(struct wil6210_priv *wil, int cid,
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u16 reason_code, bool from_event)
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__acquires(&sta->tid_rx_lock) __releases(&sta->tid_rx_lock)
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@ -474,9 +493,11 @@ int wil_priv_init(struct wil6210_priv *wil)
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mutex_init(&wil->wmi_mutex);
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mutex_init(&wil->probe_client_mutex);
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mutex_init(&wil->p2p_wdev_mutex);
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mutex_init(&wil->halp.lock);
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init_completion(&wil->wmi_ready);
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init_completion(&wil->wmi_call);
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init_completion(&wil->halp.comp);
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wil->bcast_vring = -1;
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setup_timer(&wil->connect_timer, wil_connect_timer_fn, (ulong)wil);
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@ -572,11 +593,10 @@ static inline void wil_release_cpu(struct wil6210_priv *wil)
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static void wil_set_oob_mode(struct wil6210_priv *wil, bool enable)
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{
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wil_info(wil, "%s: enable=%d\n", __func__, enable);
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if (enable) {
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if (enable)
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wil_s(wil, RGF_USER_USAGE_6, BIT_USER_OOB_MODE);
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} else {
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else
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wil_c(wil, RGF_USER_USAGE_6, BIT_USER_OOB_MODE);
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}
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}
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static int wil_target_reset(struct wil6210_priv *wil)
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@ -888,6 +908,7 @@ int wil_reset(struct wil6210_priv *wil, bool load_fw)
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wil->ap_isolate = 0;
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reinit_completion(&wil->wmi_ready);
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reinit_completion(&wil->wmi_call);
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reinit_completion(&wil->halp.comp);
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if (load_fw) {
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wil_configure_interrupt_moderation(wil);
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@ -1078,3 +1099,51 @@ int wil_find_cid(struct wil6210_priv *wil, const u8 *mac)
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return rc;
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}
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void wil_halp_vote(struct wil6210_priv *wil)
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{
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unsigned long rc;
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unsigned long to_jiffies = msecs_to_jiffies(WAIT_FOR_HALP_VOTE_MS);
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mutex_lock(&wil->halp.lock);
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wil_dbg_misc(wil, "%s: start, HALP ref_cnt (%d)\n", __func__,
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wil->halp.ref_cnt);
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if (++wil->halp.ref_cnt == 1) {
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wil6210_set_halp(wil);
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rc = wait_for_completion_timeout(&wil->halp.comp, to_jiffies);
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if (!rc)
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wil_err(wil, "%s: HALP vote timed out\n", __func__);
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else
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wil_dbg_misc(wil,
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"%s: HALP vote completed after %d ms\n",
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__func__,
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jiffies_to_msecs(to_jiffies - rc));
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}
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wil_dbg_misc(wil, "%s: end, HALP ref_cnt (%d)\n", __func__,
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wil->halp.ref_cnt);
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mutex_unlock(&wil->halp.lock);
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}
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void wil_halp_unvote(struct wil6210_priv *wil)
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{
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WARN_ON(wil->halp.ref_cnt == 0);
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mutex_lock(&wil->halp.lock);
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wil_dbg_misc(wil, "%s: start, HALP ref_cnt (%d)\n", __func__,
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wil->halp.ref_cnt);
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if (--wil->halp.ref_cnt == 0) {
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wil6210_clear_halp(wil);
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wil_dbg_misc(wil, "%s: HALP unvote\n", __func__);
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}
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wil_dbg_misc(wil, "%s: end, HALP ref_cnt (%d)\n", __func__,
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wil->halp.ref_cnt);
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mutex_unlock(&wil->halp.lock);
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}
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@ -168,6 +168,7 @@ struct RGF_ICR {
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#define RGF_DMA_EP_MISC_ICR (0x881bec) /* struct RGF_ICR */
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#define BIT_DMA_EP_MISC_ICR_RX_HTRSH BIT(0)
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#define BIT_DMA_EP_MISC_ICR_TX_NO_ACT BIT(1)
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#define BIT_DMA_EP_MISC_ICR_HALP BIT(27)
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#define BIT_DMA_EP_MISC_ICR_FW_INT(n) BIT(28+n) /* n = [0..3] */
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/* Legacy interrupt moderation control (before Sparrow v2)*/
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@ -534,6 +535,17 @@ struct pmc_ctx {
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int descriptor_size;
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};
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struct wil_halp {
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struct mutex lock; /* protect halp ref_cnt */
|
||||
unsigned int ref_cnt;
|
||||
struct completion comp;
|
||||
};
|
||||
|
||||
struct wil_blob_wrapper {
|
||||
struct wil6210_priv *wil;
|
||||
struct debugfs_blob_wrapper blob;
|
||||
};
|
||||
|
||||
struct wil6210_priv {
|
||||
struct pci_dev *pdev;
|
||||
struct wireless_dev *wdev;
|
||||
@ -606,7 +618,7 @@ struct wil6210_priv {
|
||||
atomic_t isr_count_rx, isr_count_tx;
|
||||
/* debugfs */
|
||||
struct dentry *debug;
|
||||
struct debugfs_blob_wrapper blobs[ARRAY_SIZE(fw_mapping)];
|
||||
struct wil_blob_wrapper blobs[ARRAY_SIZE(fw_mapping)];
|
||||
u8 discovery_mode;
|
||||
|
||||
void *platform_handle;
|
||||
@ -622,6 +634,10 @@ struct wil6210_priv {
|
||||
struct wireless_dev *p2p_wdev;
|
||||
struct mutex p2p_wdev_mutex; /* protect @p2p_wdev */
|
||||
struct wireless_dev *radio_wdev;
|
||||
|
||||
/* High Access Latency Policy voting */
|
||||
struct wil_halp halp;
|
||||
|
||||
};
|
||||
|
||||
#define wil_to_wiphy(i) (i->wdev->wiphy)
|
||||
@ -713,6 +729,12 @@ void wil_memcpy_fromio_32(void *dst, const volatile void __iomem *src,
|
||||
size_t count);
|
||||
void wil_memcpy_toio_32(volatile void __iomem *dst, const void *src,
|
||||
size_t count);
|
||||
void wil_memcpy_fromio_halp_vote(struct wil6210_priv *wil, void *dst,
|
||||
const volatile void __iomem *src,
|
||||
size_t count);
|
||||
void wil_memcpy_toio_halp_vote(struct wil6210_priv *wil,
|
||||
volatile void __iomem *dst,
|
||||
const void *src, size_t count);
|
||||
|
||||
void *wil_if_alloc(struct device *dev);
|
||||
void wil_if_free(struct wil6210_priv *wil);
|
||||
@ -849,4 +871,9 @@ int wil_resume(struct wil6210_priv *wil, bool is_runtime);
|
||||
int wil_fw_copy_crash_dump(struct wil6210_priv *wil, void *dest, u32 size);
|
||||
void wil_fw_core_dump(struct wil6210_priv *wil);
|
||||
|
||||
void wil_halp_vote(struct wil6210_priv *wil);
|
||||
void wil_halp_unvote(struct wil6210_priv *wil);
|
||||
void wil6210_set_halp(struct wil6210_priv *wil);
|
||||
void wil6210_clear_halp(struct wil6210_priv *wil);
|
||||
|
||||
#endif /* __WIL6210_H__ */
|
||||
|
||||
@ -194,6 +194,7 @@ static int __wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len)
|
||||
void __iomem *dst;
|
||||
void __iomem *head = wmi_addr(wil, r->head);
|
||||
uint retry;
|
||||
int rc = 0;
|
||||
|
||||
if (sizeof(cmd) + len > r->entry_size) {
|
||||
wil_err(wil, "WMI size too large: %d bytes, max is %d\n",
|
||||
@ -212,6 +213,9 @@ static int __wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len)
|
||||
wil_err(wil, "WMI head is garbage: 0x%08x\n", r->head);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
wil_halp_vote(wil);
|
||||
|
||||
/* read Tx head till it is not busy */
|
||||
for (retry = 5; retry > 0; retry--) {
|
||||
wil_memcpy_fromio_32(&d_head, head, sizeof(d_head));
|
||||
@ -221,7 +225,8 @@ static int __wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len)
|
||||
}
|
||||
if (d_head.sync != 0) {
|
||||
wil_err(wil, "WMI head busy\n");
|
||||
return -EBUSY;
|
||||
rc = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
/* next head */
|
||||
next_head = r->base + ((r->head - r->base + sizeof(d_head)) % r->size);
|
||||
@ -230,7 +235,8 @@ static int __wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len)
|
||||
for (retry = 5; retry > 0; retry--) {
|
||||
if (!test_bit(wil_status_fwready, wil->status)) {
|
||||
wil_err(wil, "WMI: cannot send command while FW not ready\n");
|
||||
return -EAGAIN;
|
||||
rc = -EAGAIN;
|
||||
goto out;
|
||||
}
|
||||
r->tail = wil_r(wil, RGF_MBOX +
|
||||
offsetof(struct wil6210_mbox_ctl, tx.tail));
|
||||
@ -240,13 +246,15 @@ static int __wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len)
|
||||
}
|
||||
if (next_head == r->tail) {
|
||||
wil_err(wil, "WMI ring full\n");
|
||||
return -EBUSY;
|
||||
rc = -EBUSY;
|
||||
goto out;
|
||||
}
|
||||
dst = wmi_buffer(wil, d_head.addr);
|
||||
if (!dst) {
|
||||
wil_err(wil, "invalid WMI buffer: 0x%08x\n",
|
||||
le32_to_cpu(d_head.addr));
|
||||
return -EINVAL;
|
||||
rc = -EAGAIN;
|
||||
goto out;
|
||||
}
|
||||
cmd.hdr.seq = cpu_to_le16(++wil->wmi_seq);
|
||||
/* set command */
|
||||
@ -269,7 +277,9 @@ static int __wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len)
|
||||
wil_w(wil, RGF_USER_USER_ICR + offsetof(struct RGF_ICR, ICS),
|
||||
SW_INT_MBOX);
|
||||
|
||||
return 0;
|
||||
out:
|
||||
wil_halp_unvote(wil);
|
||||
return rc;
|
||||
}
|
||||
|
||||
int wmi_send(struct wil6210_priv *wil, u16 cmdid, void *buf, u16 len)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user