mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 21:15:44 +07:00
drm/i915/debugfs: move uC printers and update debugfs file names
Move the printers to the respective files for clarity. The
guc_load_status debugfs has been squashed in the guc_info one, has
having separate ones wasn't very useful. The HuC debugfs has been
renamed huc_info to match.
v2: keep printing HUC_STATUS2 (Tony), avoid const->non-const
container_of (Jani)
Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
Cc: Tony Ye <tony.ye@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200326181121.16869-5-daniele.ceraolospurio@intel.com
This commit is contained in:
Daniele Ceraolo Spurio
Chris Wilson
parent
801a0caa62
commit
34904bd64a
@ -723,3 +723,47 @@ int intel_guc_allocate_and_map_vma(struct intel_guc *guc, u32 size,
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return 0;
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}
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/**
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* intel_guc_load_status - dump information about GuC load status
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* @guc: the GuC
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* @p: the &drm_printer
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*
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* Pretty printer for GuC load status.
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*/
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void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p)
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{
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struct intel_gt *gt = guc_to_gt(guc);
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struct intel_uncore *uncore = gt->uncore;
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intel_wakeref_t wakeref;
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if (!intel_guc_is_supported(guc)) {
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drm_printf(p, "GuC not supported\n");
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return;
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}
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if (!intel_guc_is_wanted(guc)) {
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drm_printf(p, "GuC disabled\n");
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return;
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}
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intel_uc_fw_dump(&guc->fw, p);
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with_intel_runtime_pm(uncore->rpm, wakeref) {
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u32 status = intel_uncore_read(uncore, GUC_STATUS);
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u32 i;
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drm_printf(p, "\nGuC status 0x%08x:\n", status);
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drm_printf(p, "\tBootrom status = 0x%x\n",
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(status & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
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drm_printf(p, "\tuKernel status = 0x%x\n",
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(status & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
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drm_printf(p, "\tMIA Core status = 0x%x\n",
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(status & GS_MIA_MASK) >> GS_MIA_SHIFT);
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drm_puts(p, "\nScratch registers:\n");
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for (i = 0; i < 16; i++) {
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drm_printf(p, "\t%2d: \t0x%x\n",
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i, intel_uncore_read(uncore, SOFT_SCRATCH(i)));
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}
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}
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}
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@ -190,4 +190,6 @@ static inline void intel_guc_disable_msg(struct intel_guc *guc, u32 mask)
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int intel_guc_reset_engine(struct intel_guc *guc,
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struct intel_engine_cs *engine);
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void intel_guc_load_status(struct intel_guc *guc, struct drm_printer *p);
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#endif
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@ -672,3 +672,95 @@ void intel_guc_log_handle_flush_event(struct intel_guc_log *log)
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{
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queue_work(system_highpri_wq, &log->relay.flush_work);
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}
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static const char *
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stringify_guc_log_type(enum guc_log_buffer_type type)
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{
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switch (type) {
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case GUC_ISR_LOG_BUFFER:
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return "ISR";
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case GUC_DPC_LOG_BUFFER:
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return "DPC";
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case GUC_CRASH_DUMP_LOG_BUFFER:
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return "CRASH";
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default:
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MISSING_CASE(type);
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}
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return "";
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}
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/**
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* intel_guc_log_info - dump information about GuC log relay
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* @guc: the GuC
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* @p: the &drm_printer
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*
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* Pretty printer for GuC log info
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*/
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void intel_guc_log_info(struct intel_guc_log *log, struct drm_printer *p)
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{
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enum guc_log_buffer_type type;
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if (!intel_guc_log_relay_created(log)) {
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drm_puts(p, "GuC log relay not created\n");
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return;
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}
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drm_puts(p, "GuC logging stats:\n");
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drm_printf(p, "\tRelay full count: %u\n", log->relay.full_count);
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for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
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drm_printf(p, "\t%s:\tflush count %10u, overflow count %10u\n",
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stringify_guc_log_type(type),
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log->stats[type].flush,
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log->stats[type].sampled_overflow);
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}
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}
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/**
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* intel_guc_log_dump - dump the contents of the GuC log
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* @log: the GuC log
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* @p: the &drm_printer
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* @dump_load_err: dump the log saved on GuC load error
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*
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* Pretty printer for the GuC log
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*/
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int intel_guc_log_dump(struct intel_guc_log *log, struct drm_printer *p,
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bool dump_load_err)
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{
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struct intel_guc *guc = log_to_guc(log);
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struct intel_uc *uc = container_of(guc, struct intel_uc, guc);
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struct drm_i915_gem_object *obj = NULL;
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u32 *map;
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int i = 0;
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if (!intel_guc_is_supported(guc))
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return -ENODEV;
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if (dump_load_err)
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obj = uc->load_err_log;
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else if (guc->log.vma)
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obj = guc->log.vma->obj;
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if (!obj)
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return 0;
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map = i915_gem_object_pin_map(obj, I915_MAP_WC);
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if (IS_ERR(map)) {
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DRM_DEBUG("Failed to pin object\n");
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drm_puts(p, "(log data unaccessible)\n");
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return PTR_ERR(map);
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}
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for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
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drm_printf(p, "0x%08x 0x%08x 0x%08x 0x%08x\n",
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*(map + i), *(map + i + 1),
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*(map + i + 2), *(map + i + 3));
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drm_puts(p, "\n");
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i915_gem_object_unpin_map(obj);
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return 0;
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}
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@ -79,4 +79,8 @@ static inline u32 intel_guc_log_get_level(struct intel_guc_log *log)
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return log->level;
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}
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void intel_guc_log_info(struct intel_guc_log *log, struct drm_printer *p);
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int intel_guc_log_dump(struct intel_guc_log *log, struct drm_printer *p,
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bool dump_load_err);
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#endif
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@ -218,3 +218,32 @@ int intel_huc_check_status(struct intel_huc *huc)
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return (status & huc->status.mask) == huc->status.value;
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}
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/**
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* intel_huc_load_status - dump information about HuC load status
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* @huc: the HuC
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* @p: the &drm_printer
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*
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* Pretty printer for HuC load status.
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*/
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void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p)
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{
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struct intel_gt *gt = huc_to_gt(huc);
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intel_wakeref_t wakeref;
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if (!intel_huc_is_supported(huc)) {
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drm_printf(p, "HuC not supported\n");
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return;
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}
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if (!intel_huc_is_wanted(huc)) {
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drm_printf(p, "HuC disabled\n");
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return;
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}
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intel_uc_fw_dump(&huc->fw, p);
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with_intel_runtime_pm(gt->uncore->rpm, wakeref)
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drm_printf(p, "\nHuC status 0x%08x:\n",
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intel_uncore_read(gt->uncore, HUC_STATUS2));
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}
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@ -57,4 +57,6 @@ static inline bool intel_huc_is_authenticated(struct intel_huc *huc)
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return intel_uc_fw_is_running(&huc->fw);
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}
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void intel_huc_load_status(struct intel_huc *huc, struct drm_printer *p);
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#endif
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@ -1251,105 +1251,32 @@ static int i915_llc(struct seq_file *m, void *data)
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return 0;
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}
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static int i915_huc_load_status_info(struct seq_file *m, void *data)
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static int i915_huc_info(struct seq_file *m, void *data)
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{
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struct drm_i915_private *dev_priv = node_to_i915(m->private);
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intel_wakeref_t wakeref;
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struct drm_printer p;
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struct intel_huc *huc = &dev_priv->gt.uc.huc;
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struct drm_printer p = drm_seq_file_printer(m);
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if (!HAS_GT_UC(dev_priv))
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if (!intel_huc_is_supported(huc))
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return -ENODEV;
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p = drm_seq_file_printer(m);
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intel_uc_fw_dump(&dev_priv->gt.uc.huc.fw, &p);
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with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref)
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seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2));
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intel_huc_load_status(huc, &p);
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return 0;
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}
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static int i915_guc_load_status_info(struct seq_file *m, void *data)
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{
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struct drm_i915_private *dev_priv = node_to_i915(m->private);
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intel_wakeref_t wakeref;
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struct drm_printer p;
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if (!HAS_GT_UC(dev_priv))
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return -ENODEV;
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p = drm_seq_file_printer(m);
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intel_uc_fw_dump(&dev_priv->gt.uc.guc.fw, &p);
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with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
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u32 tmp = I915_READ(GUC_STATUS);
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u32 i;
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seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
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seq_printf(m, "\tBootrom status = 0x%x\n",
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(tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
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seq_printf(m, "\tuKernel status = 0x%x\n",
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(tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
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seq_printf(m, "\tMIA Core status = 0x%x\n",
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(tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
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seq_puts(m, "\nScratch registers:\n");
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for (i = 0; i < 16; i++) {
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seq_printf(m, "\t%2d: \t0x%x\n",
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i, I915_READ(SOFT_SCRATCH(i)));
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}
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}
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return 0;
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}
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static const char *
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stringify_guc_log_type(enum guc_log_buffer_type type)
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{
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switch (type) {
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case GUC_ISR_LOG_BUFFER:
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return "ISR";
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case GUC_DPC_LOG_BUFFER:
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return "DPC";
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case GUC_CRASH_DUMP_LOG_BUFFER:
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return "CRASH";
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default:
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MISSING_CASE(type);
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}
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return "";
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}
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static void i915_guc_log_info(struct seq_file *m, struct intel_guc_log *log)
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{
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enum guc_log_buffer_type type;
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if (!intel_guc_log_relay_created(log)) {
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seq_puts(m, "GuC log relay not created\n");
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return;
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}
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seq_puts(m, "GuC logging stats:\n");
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seq_printf(m, "\tRelay full count: %u\n",
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log->relay.full_count);
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for (type = GUC_ISR_LOG_BUFFER; type < GUC_MAX_LOG_BUFFER; type++) {
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seq_printf(m, "\t%s:\tflush count %10u, overflow count %10u\n",
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stringify_guc_log_type(type),
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log->stats[type].flush,
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log->stats[type].sampled_overflow);
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}
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}
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static int i915_guc_info(struct seq_file *m, void *data)
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{
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struct drm_i915_private *dev_priv = node_to_i915(m->private);
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struct intel_uc *uc = &dev_priv->gt.uc;
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struct intel_guc *guc = &dev_priv->gt.uc.guc;
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struct drm_printer p = drm_seq_file_printer(m);
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if (!intel_uc_uses_guc(uc))
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if (!intel_guc_is_supported(guc))
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return -ENODEV;
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i915_guc_log_info(m, &uc->guc.log);
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intel_guc_load_status(guc, &p);
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drm_puts(&p, "\n");
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intel_guc_log_info(&guc->log, &p);
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/* Add more as required ... */
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@ -1360,39 +1287,14 @@ static int i915_guc_log_dump(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = m->private;
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struct drm_i915_private *dev_priv = node_to_i915(node);
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struct intel_guc *guc = &dev_priv->gt.uc.guc;
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bool dump_load_err = !!node->info_ent->data;
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struct drm_i915_gem_object *obj = NULL;
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u32 *log;
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int i = 0;
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struct drm_printer p = drm_seq_file_printer(m);
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if (!HAS_GT_UC(dev_priv))
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if (!intel_guc_is_supported(guc))
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return -ENODEV;
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if (dump_load_err)
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obj = dev_priv->gt.uc.load_err_log;
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else if (dev_priv->gt.uc.guc.log.vma)
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obj = dev_priv->gt.uc.guc.log.vma->obj;
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if (!obj)
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return 0;
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log = i915_gem_object_pin_map(obj, I915_MAP_WC);
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if (IS_ERR(log)) {
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DRM_DEBUG("Failed to pin object\n");
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seq_puts(m, "(log data unaccessible)\n");
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return PTR_ERR(log);
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}
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for (i = 0; i < obj->base.size / sizeof(u32); i += 4)
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seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
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*(log + i), *(log + i + 1),
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*(log + i + 2), *(log + i + 3));
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seq_putc(m, '\n');
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i915_gem_object_unpin_map(obj);
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return 0;
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return intel_guc_log_dump(&guc->log, &p, dump_load_err);
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}
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static int i915_guc_log_level_get(void *data, u64 *val)
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@ -2088,10 +1990,9 @@ static const struct drm_info_list i915_debugfs_list[] = {
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{"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
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{"i915_gem_interrupt", i915_interrupt_info, 0},
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{"i915_guc_info", i915_guc_info, 0},
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{"i915_guc_load_status", i915_guc_load_status_info, 0},
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{"i915_guc_log_dump", i915_guc_log_dump, 0},
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{"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
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{"i915_huc_load_status", i915_huc_load_status_info, 0},
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{"i915_huc_info", i915_huc_info, 0},
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{"i915_frequency_info", i915_frequency_info, 0},
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{"i915_ring_freq_table", i915_ring_freq_table, 0},
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{"i915_context_status", i915_context_status, 0},
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