mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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serial: stm32: adding dma support
This patch adds dma mode support for rx and tx with pio mode as fallback in case of dma error. Signed-off-by: Gerald Baeza <gerald.baeza@st.com> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Alexandre TORGUE
Greg Kroah-Hartman
parent
3fa047fde4
commit
3489187204
@ -11,26 +11,31 @@
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#define SUPPORT_SYSRQ
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#endif
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#include <linux/module.h>
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#include <linux/serial.h>
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#include <linux/clk.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/pm_runtime.h>
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#include <linux/dma-direction.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/serial_core.h>
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#include <linux/clk.h>
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#include <linux/serial.h>
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#include <linux/spinlock.h>
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#include <linux/sysrq.h>
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#include <linux/tty_flip.h>
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#include <linux/tty.h>
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#include "stm32-usart.h"
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static void stm32_stop_tx(struct uart_port *port);
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static void stm32_transmit_chars(struct uart_port *port);
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static inline struct stm32_port *to_stm32_port(struct uart_port *port)
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{
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@ -55,7 +60,48 @@ static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
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writel_relaxed(val, port->membase + reg);
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}
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static void stm32_receive_chars(struct uart_port *port)
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int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
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bool threaded)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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enum dma_status status;
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struct dma_tx_state state;
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*sr = readl_relaxed(port->membase + ofs->isr);
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if (threaded && stm32_port->rx_ch) {
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status = dmaengine_tx_status(stm32_port->rx_ch,
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stm32_port->rx_ch->cookie,
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&state);
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if ((status == DMA_IN_PROGRESS) &&
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(*last_res != state.residue))
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return 1;
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else
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return 0;
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} else if (*sr & USART_SR_RXNE) {
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return 1;
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}
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return 0;
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}
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unsigned long stm32_get_char(struct uart_port *port, u32 *sr, int *last_res)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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unsigned long c;
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if (stm32_port->rx_ch) {
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c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
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if ((*last_res) == 0)
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*last_res = RX_BUF_L;
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return c;
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} else {
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return readl_relaxed(port->membase + ofs->rdr);
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}
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}
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static void stm32_receive_chars(struct uart_port *port, bool threaded)
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{
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struct tty_port *tport = &port->state->port;
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struct stm32_port *stm32_port = to_stm32_port(port);
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@ -63,13 +109,14 @@ static void stm32_receive_chars(struct uart_port *port)
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unsigned long c;
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u32 sr;
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char flag;
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static int last_res = RX_BUF_L;
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if (port->irq_wake)
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pm_wakeup_event(tport->tty->dev, 0);
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while ((sr = readl_relaxed(port->membase + ofs->isr)) & USART_SR_RXNE) {
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while (stm32_pending_rx(port, &sr, &last_res, threaded)) {
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sr |= USART_SR_DUMMY_RX;
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c = readl_relaxed(port->membase + ofs->rdr);
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c = stm32_get_char(port, &sr, &last_res);
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flag = TTY_NORMAL;
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port->icount.rx++;
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@ -110,6 +157,124 @@ static void stm32_receive_chars(struct uart_port *port)
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spin_lock(&port->lock);
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}
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static void stm32_tx_dma_complete(void *arg)
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{
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struct uart_port *port = arg;
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struct stm32_port *stm32port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
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unsigned int isr;
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int ret;
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ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
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isr,
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(isr & USART_SR_TC),
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10, 100000);
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if (ret)
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dev_err(port->dev, "terminal count not set\n");
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if (ofs->icr == UNDEF_REG)
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stm32_clr_bits(port, ofs->isr, USART_SR_TC);
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else
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stm32_set_bits(port, ofs->icr, USART_CR_TC);
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stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
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stm32port->tx_dma_busy = false;
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/* Let's see if we have pending data to send */
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stm32_transmit_chars(port);
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}
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static void stm32_transmit_chars_pio(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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struct circ_buf *xmit = &port->state->xmit;
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unsigned int isr;
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int ret;
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if (stm32_port->tx_dma_busy) {
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stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
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stm32_port->tx_dma_busy = false;
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}
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ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
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isr,
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(isr & USART_SR_TXE),
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10, 100);
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if (ret)
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dev_err(port->dev, "tx empty not set\n");
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stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
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writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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}
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static void stm32_transmit_chars_dma(struct uart_port *port)
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{
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struct stm32_port *stm32port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
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struct circ_buf *xmit = &port->state->xmit;
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struct dma_async_tx_descriptor *desc = NULL;
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dma_cookie_t cookie;
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unsigned int count, i;
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if (stm32port->tx_dma_busy)
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return;
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stm32port->tx_dma_busy = true;
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count = uart_circ_chars_pending(xmit);
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if (count > TX_BUF_L)
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count = TX_BUF_L;
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if (xmit->tail < xmit->head) {
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memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
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} else {
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size_t one = UART_XMIT_SIZE - xmit->tail;
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size_t two;
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if (one > count)
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one = count;
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two = count - one;
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memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
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if (two)
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memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
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}
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desc = dmaengine_prep_slave_single(stm32port->tx_ch,
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stm32port->tx_dma_buf,
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count,
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DMA_MEM_TO_DEV,
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DMA_PREP_INTERRUPT);
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if (!desc) {
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for (i = count; i > 0; i--)
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stm32_transmit_chars_pio(port);
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return;
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}
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desc->callback = stm32_tx_dma_complete;
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desc->callback_param = port;
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/* Push current DMA TX transaction in the pending queue */
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cookie = dmaengine_submit(desc);
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/* Issue pending DMA TX requests */
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dma_async_issue_pending(stm32port->tx_ch);
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stm32_clr_bits(port, ofs->isr, USART_SR_TC);
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stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
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xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
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port->icount.tx += count;
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}
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static void stm32_transmit_chars(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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@ -117,9 +282,13 @@ static void stm32_transmit_chars(struct uart_port *port)
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struct circ_buf *xmit = &port->state->xmit;
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if (port->x_char) {
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if (stm32_port->tx_dma_busy)
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stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
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writel_relaxed(port->x_char, port->membase + ofs->tdr);
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port->x_char = 0;
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port->icount.tx++;
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if (stm32_port->tx_dma_busy)
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stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
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return;
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}
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@ -133,9 +302,10 @@ static void stm32_transmit_chars(struct uart_port *port)
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return;
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}
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writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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if (stm32_port->tx_ch)
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stm32_transmit_chars_dma(port);
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else
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stm32_transmit_chars_pio(port);
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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@ -151,16 +321,30 @@ static irqreturn_t stm32_interrupt(int irq, void *ptr)
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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u32 sr;
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spin_lock(&port->lock);
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sr = readl_relaxed(port->membase + ofs->isr);
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if (sr & USART_SR_RXNE)
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stm32_receive_chars(port);
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if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
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stm32_receive_chars(port, false);
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if (sr & USART_SR_TXE)
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if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
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stm32_transmit_chars(port);
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if (stm32_port->rx_ch)
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return IRQ_WAKE_THREAD;
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else
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return IRQ_HANDLED;
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}
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static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
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{
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struct uart_port *port = ptr;
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struct stm32_port *stm32_port = to_stm32_port(port);
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spin_lock(&port->lock);
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if (stm32_port->rx_ch)
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stm32_receive_chars(port, true);
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spin_unlock(&port->lock);
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return IRQ_HANDLED;
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@ -203,14 +387,12 @@ static void stm32_stop_tx(struct uart_port *port)
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/* There are probably characters waiting to be transmitted. */
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static void stm32_start_tx(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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struct circ_buf *xmit = &port->state->xmit;
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if (uart_circ_empty(xmit))
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return;
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stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE | USART_CR1_TE);
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stm32_transmit_chars(port);
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}
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/* Throttle the remote when input buffer is about to overflow. */
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@ -259,7 +441,9 @@ static int stm32_startup(struct uart_port *port)
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u32 val;
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int ret;
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ret = request_irq(port->irq, stm32_interrupt, 0, name, port);
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ret = request_threaded_irq(port->irq, stm32_interrupt,
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stm32_threaded_interrupt,
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IRQF_NO_SUSPEND, name, port);
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if (ret)
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return ret;
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@ -376,6 +560,9 @@ static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
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if ((termios->c_cflag & CREAD) == 0)
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port->ignore_status_mask |= USART_SR_DUMMY_RX;
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if (stm32_port->rx_ch)
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cr3 |= USART_CR3_DMAR;
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writel_relaxed(cr3, port->membase + ofs->cr3);
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writel_relaxed(cr2, port->membase + ofs->cr2);
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writel_relaxed(cr1, port->membase + ofs->cr1);
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@ -523,6 +710,129 @@ static const struct of_device_id stm32_match[] = {
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MODULE_DEVICE_TABLE(of, stm32_match);
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#endif
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static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
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struct platform_device *pdev)
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{
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struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
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struct uart_port *port = &stm32port->port;
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struct device *dev = &pdev->dev;
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struct dma_slave_config config;
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struct dma_async_tx_descriptor *desc = NULL;
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dma_cookie_t cookie;
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int ret;
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/* Request DMA RX channel */
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stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
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if (!stm32port->rx_ch) {
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dev_info(dev, "rx dma alloc failed\n");
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return -ENODEV;
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}
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stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
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&stm32port->rx_dma_buf,
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GFP_KERNEL);
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if (!stm32port->rx_buf) {
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ret = -ENOMEM;
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goto alloc_err;
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}
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/* Configure DMA channel */
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memset(&config, 0, sizeof(config));
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config.src_addr = (dma_addr_t)port->membase + ofs->rdr;
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config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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ret = dmaengine_slave_config(stm32port->rx_ch, &config);
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if (ret < 0) {
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dev_err(dev, "rx dma channel config failed\n");
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ret = -ENODEV;
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goto config_err;
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}
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/* Prepare a DMA cyclic transaction */
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desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
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stm32port->rx_dma_buf,
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RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT);
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if (!desc) {
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dev_err(dev, "rx dma prep cyclic failed\n");
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ret = -ENODEV;
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goto config_err;
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}
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/* No callback as dma buffer is drained on usart interrupt */
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desc->callback = NULL;
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desc->callback_param = NULL;
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/* Push current DMA transaction in the pending queue */
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cookie = dmaengine_submit(desc);
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/* Issue pending DMA requests */
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dma_async_issue_pending(stm32port->rx_ch);
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return 0;
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config_err:
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dma_free_coherent(&pdev->dev,
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RX_BUF_L, stm32port->rx_buf,
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stm32port->rx_dma_buf);
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alloc_err:
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dma_release_channel(stm32port->rx_ch);
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stm32port->rx_ch = NULL;
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return ret;
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}
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static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
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struct platform_device *pdev)
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{
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struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
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struct uart_port *port = &stm32port->port;
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struct device *dev = &pdev->dev;
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struct dma_slave_config config;
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int ret;
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stm32port->tx_dma_busy = false;
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/* Request DMA TX channel */
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stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
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if (!stm32port->tx_ch) {
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dev_info(dev, "tx dma alloc failed\n");
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return -ENODEV;
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}
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||||
stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
|
||||
&stm32port->tx_dma_buf,
|
||||
GFP_KERNEL);
|
||||
if (!stm32port->tx_buf) {
|
||||
ret = -ENOMEM;
|
||||
goto alloc_err;
|
||||
}
|
||||
|
||||
/* Configure DMA channel */
|
||||
memset(&config, 0, sizeof(config));
|
||||
config.dst_addr = (dma_addr_t)port->membase + ofs->tdr;
|
||||
config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
|
||||
|
||||
ret = dmaengine_slave_config(stm32port->tx_ch, &config);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "tx dma channel config failed\n");
|
||||
ret = -ENODEV;
|
||||
goto config_err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
config_err:
|
||||
dma_free_coherent(&pdev->dev,
|
||||
TX_BUF_L, stm32port->tx_buf,
|
||||
stm32port->tx_dma_buf);
|
||||
|
||||
alloc_err:
|
||||
dma_release_channel(stm32port->tx_ch);
|
||||
stm32port->tx_ch = NULL;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int stm32_serial_probe(struct platform_device *pdev)
|
||||
{
|
||||
const struct of_device_id *match;
|
||||
@ -547,6 +857,14 @@ static int stm32_serial_probe(struct platform_device *pdev)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = stm32_of_dma_rx_probe(stm32port, pdev);
|
||||
if (ret)
|
||||
dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
|
||||
|
||||
ret = stm32_of_dma_tx_probe(stm32port, pdev);
|
||||
if (ret)
|
||||
dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
|
||||
|
||||
platform_set_drvdata(pdev, &stm32port->port);
|
||||
|
||||
return 0;
|
||||
@ -556,6 +874,27 @@ static int stm32_serial_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct uart_port *port = platform_get_drvdata(pdev);
|
||||
struct stm32_port *stm32_port = to_stm32_port(port);
|
||||
struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
|
||||
|
||||
stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
|
||||
|
||||
if (stm32_port->rx_ch)
|
||||
dma_release_channel(stm32_port->rx_ch);
|
||||
|
||||
if (stm32_port->rx_dma_buf)
|
||||
dma_free_coherent(&pdev->dev,
|
||||
RX_BUF_L, stm32_port->rx_buf,
|
||||
stm32_port->rx_dma_buf);
|
||||
|
||||
stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
|
||||
|
||||
if (stm32_port->tx_ch)
|
||||
dma_release_channel(stm32_port->tx_ch);
|
||||
|
||||
if (stm32_port->tx_dma_buf)
|
||||
dma_free_coherent(&pdev->dev,
|
||||
TX_BUF_L, stm32_port->tx_buf,
|
||||
stm32_port->tx_dma_buf);
|
||||
|
||||
clk_disable_unprepare(stm32_port->clk);
|
||||
|
||||
|
||||
@ -99,6 +99,9 @@ struct stm32_usart_info stm32f7_info = {
|
||||
/* Dummy bits */
|
||||
#define USART_SR_DUMMY_RX BIT(16)
|
||||
|
||||
/* USART_ICR (F7) */
|
||||
#define USART_CR_TC BIT(6)
|
||||
|
||||
/* USART_DR */
|
||||
#define USART_DR_MASK GENMASK(8, 0)
|
||||
|
||||
@ -204,10 +207,21 @@ struct stm32_usart_info stm32f7_info = {
|
||||
#define STM32_SERIAL_NAME "ttyS"
|
||||
#define STM32_MAX_PORTS 6
|
||||
|
||||
#define RX_BUF_L 200 /* dma rx buffer length */
|
||||
#define RX_BUF_P RX_BUF_L /* dma rx buffer period */
|
||||
#define TX_BUF_L 200 /* dma tx buffer length */
|
||||
|
||||
struct stm32_port {
|
||||
struct uart_port port;
|
||||
struct clk *clk;
|
||||
struct stm32_usart_info *info;
|
||||
struct dma_chan *rx_ch; /* dma rx channel */
|
||||
dma_addr_t rx_dma_buf; /* dma rx buffer bus address */
|
||||
unsigned char *rx_buf; /* dma rx buffer cpu address */
|
||||
struct dma_chan *tx_ch; /* dma tx channel */
|
||||
dma_addr_t tx_dma_buf; /* dma tx buffer bus address */
|
||||
unsigned char *tx_buf; /* dma tx buffer cpu address */
|
||||
bool tx_dma_busy; /* dma tx busy */
|
||||
bool hw_flow_control;
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user