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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 10:06:00 +07:00
mt76x0: remove mt76x0_burst_write_regs()
We don't need to use custom burst write regs via MCU, we can use generic mt76_wr_copy() for the same purpose. Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com> Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@redhat.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
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@ -249,7 +249,7 @@ static void mt76x0_init_mac_registers(struct mt76x0_dev *dev)
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static int mt76x0_init_wcid_mem(struct mt76x0_dev *dev)
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{
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u32 *vals;
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int i, ret;
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int i;
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vals = kmalloc(sizeof(*vals) * MT76_N_WCIDS * 2, GFP_KERNEL);
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if (!vals)
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@ -260,25 +260,22 @@ static int mt76x0_init_wcid_mem(struct mt76x0_dev *dev)
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vals[i * 2 + 1] = 0x00ffffff;
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}
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ret = mt76x0_burst_write_regs(dev, MT_WCID_ADDR_BASE,
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vals, MT76_N_WCIDS * 2);
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mt76_wr_copy(dev, MT_WCID_ADDR_BASE, vals, MT76_N_WCIDS * 2);
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kfree(vals);
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return ret;
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return 0;
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}
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static int mt76x0_init_key_mem(struct mt76x0_dev *dev)
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static void mt76x0_init_key_mem(struct mt76x0_dev *dev)
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{
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u32 vals[4] = {};
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return mt76x0_burst_write_regs(dev, MT_SKEY_MODE_BASE_0,
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vals, ARRAY_SIZE(vals));
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mt76_wr_copy(dev, MT_SKEY_MODE_BASE_0, vals, ARRAY_SIZE(vals));
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}
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static int mt76x0_init_wcid_attr_mem(struct mt76x0_dev *dev)
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{
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u32 *vals;
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int i, ret;
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int i;
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vals = kmalloc(sizeof(*vals) * MT76_N_WCIDS * 2, GFP_KERNEL);
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if (!vals)
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@ -287,11 +284,9 @@ static int mt76x0_init_wcid_attr_mem(struct mt76x0_dev *dev)
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for (i = 0; i < MT76_N_WCIDS * 2; i++)
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vals[i] = 1;
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ret = mt76x0_burst_write_regs(dev, MT_WCID_ATTR_BASE,
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vals, MT76_N_WCIDS * 2);
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mt76_wr_copy(dev, MT_WCID_ATTR_BASE, vals, MT76_N_WCIDS * 2);
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kfree(vals);
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return ret;
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return 0;
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}
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static void mt76x0_reset_counters(struct mt76x0_dev *dev)
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@ -443,9 +438,7 @@ int mt76x0_init_hardware(struct mt76x0_dev *dev)
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if (ret)
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return ret;
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ret = mt76x0_init_key_mem(dev);
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if (ret)
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return ret;
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mt76x0_init_key_mem(dev);
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ret = mt76x0_init_wcid_attr_mem(dev);
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if (ret)
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@ -77,35 +77,6 @@ mt76x0_mcu_calibrate(struct mt76x0_dev *dev, enum mcu_calibrate cal, u32 val)
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return mt76_mcu_send_msg(dev, skb, CMD_CALIBRATION_OP, true);
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}
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int mt76x0_burst_write_regs(struct mt76x0_dev *dev, u32 offset,
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const u32 *data, int n)
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{
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const int max_regs_per_cmd = MT_INBAND_PACKET_MAX_LEN / 4 - 1;
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struct sk_buff *skb;
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int cnt, i, ret;
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if (!n)
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return 0;
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cnt = min(max_regs_per_cmd, n);
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skb = alloc_skb(cnt * 4 + MT_DMA_HDR_LEN + 4, GFP_KERNEL);
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if (!skb)
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return -ENOMEM;
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skb_reserve(skb, MT_DMA_HDR_LEN);
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skb_put_le32(skb, MT_MCU_MEMMAP_WLAN + offset);
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for (i = 0; i < cnt; i++)
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skb_put_le32(skb, data[i]);
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ret = mt76_mcu_send_msg(dev, skb, CMD_BURST_WRITE, cnt == n);
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if (ret)
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return ret;
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return mt76x0_burst_write_regs(dev, offset + cnt * 4,
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data + cnt, n - cnt);
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}
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struct mt76_fw_header {
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__le32 ilm_len;
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__le32 dlm_len;
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@ -126,9 +126,6 @@ void mt76x0_init_debugfs(struct mt76x0_dev *dev);
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#define mt76_rmw_field(_dev, _reg, _field, _val) \
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mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
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int mt76x0_burst_write_regs(struct mt76x0_dev *dev, u32 offset,
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const u32 *data, int n);
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/* Init */
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struct mt76x0_dev *
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mt76x0_alloc_device(struct device *pdev, const struct mt76_driver_ops *drv_ops);
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