ARM64: DT: Hisilicon SoCs DT updates for 5.5

- add Mali450 MP4 GPU node in the hi6220 SoC
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJduUeEAAoJEAvIV27ZiWZclB0P/2E2SUD595mir9+49zNgrlqx
 JS559GOtzK096kmfQQ88tvB5BC2AulZX99tiC31a8Iy/qGdG2iXTnzJnuH6oCvT7
 sVMsFz+8tq6UB+VtVBCRrUvaQogqLD13hNQacqBENrD/jM2mrYbIfnYYUyftwZrA
 NJwS2fxQhSIRrFYKDSRSxey2a/8C8nfpnp3+9M2pzX3OTHhjfBKjPY1qrlIK9CNf
 IuAWYyTxZAolMNwS68di35fMv36PEzbeVnUcMMaeCG4j/u8IOzjEHibI2jzkncm8
 oJhXyzQ5T9g/qHXy8nlSB26XxIP/9cDWEKeSpZdAqYnxt78BDHFmHB2W5f6xWdXj
 b3NkclmtKyJwEfDdTgB5gbVabSdWrfNEQ2HQ/FAqCuidhxJjBZdEyc7VM2Bq0Oqs
 GtCZDGE+kShDFIr2jH8FmcF/dtbUT8h1v/JkfcMSuzGHyHE8m0cj8i7yGUEHcC/F
 p6Dmrg0pUaUfs+qQ46r0yddRop+EdS/JTYGN0TYagd4vO4V9PQh8nGPXl4fjp0tK
 29pRyO2KRxPgQP+ZRkX/DNWGutEU9M50umIXkri2SWygTU6Jjbk2VQFbiOdmeVpB
 IhIkKqDA5OY+HCxapr4zCDUYUSXydmzDqWYbGtL8p5a47tBBzvkwlNvz/gnPPF1y
 B+f5Dn76zel481ehTBHY
 =cPoz
 -----END PGP SIGNATURE-----

Merge tag 'hisi-arm64-dt-for-5.5' of git://github.com/hisilicon/linux-hisi into arm/dt

ARM64: DT: Hisilicon SoCs DT updates for 5.5

- add Mali450 MP4 GPU node in the hi6220 SoC

* tag 'hisi-arm64-dt-for-5.5' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hisilicon: Add Mali-450 MP4 GPU DT entry

Link: https://lore.kernel.org/r/5DB95AAB.8060405@hisilicon.com
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson 2019-11-03 16:56:23 -08:00
commit 32f714d30f

View File

@ -260,6 +260,7 @@ ao_ctrl: ao_ctrl@f7800000 {
compatible = "hisilicon,hi6220-aoctrl", "syscon";
reg = <0x0 0xf7800000 0x0 0x2000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
sys_ctrl: sys_ctrl@f7030000 {
@ -1021,6 +1022,43 @@ debug@f65d6000 {
clock-names = "apb_pclk";
cpu = <&cpu7>;
};
mali: gpu@f4080000 {
compatible = "hisilicon,hi6220-mali", "arm,mali-450";
reg = <0x0 0xf4080000 0x0 0x00040000>;
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp",
"gpmmu",
"pp",
"pp0",
"ppmmu0",
"pp1",
"ppmmu1",
"pp2",
"ppmmu2",
"pp3",
"ppmmu3";
clocks = <&media_ctrl HI6220_G3D_CLK>,
<&media_ctrl HI6220_G3D_PCLK>;
clock-names = "core", "bus";
assigned-clocks = <&media_ctrl HI6220_G3D_CLK>,
<&media_ctrl HI6220_G3D_PCLK>;
assigned-clock-rates = <500000000>, <144000000>;
reset-names = "ao_g3d", "media_g3d";
resets = <&ao_ctrl AO_G3D>, <&media_ctrl MEDIA_G3D>;
};
};
};