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arm64: dts: renesas: r8a77990: ebisu: Add and enable CAN,FD device nodes

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This patch adds CAN0,1 and CANFD device nodes for the r8a77990 SoC
and enables CANFD connected to CN10 on the E3 Ebisu board using the
R8A77990 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This commit is contained in:
Marek Vasut 2018-11-18 18:34:24 +01:00 committed by Simon Horman
parent 55db8ac68d
commit 327d1f3208
2 changed files with 79 additions and 0 deletions
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15
arch/arm64/boot/dts/renesas/r8a77990-ebisu.dts
View File

@ -260,6 +260,16 @@ phy0: ethernet-phy@0 {
}; };
}; };
&canfd {
pinctrl-0 = <&canfd0_pins>;
pinctrl-names = "default";
status = "okay";
channel0 {
status = "okay";
};
};
&csi40 { &csi40 {
status = "okay"; status = "okay";
@ -460,6 +470,11 @@ mux {
}; };
}; };
canfd0_pins: canfd0 {
groups = "canfd0_data";
function = "canfd0";
};
du_pins: du { du_pins: du {
groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0"; groups = "du_rgb888", "du_sync", "du_disp", "du_clk_out_0";
function = "du"; function = "du";

64
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View File

@ -48,6 +48,13 @@ audio_clk_c: audio_clk_c {
clock-frequency = <0>; clock-frequency = <0>;
}; };
/* External CAN clock - to be overridden by boards that provide it */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <0>;
};
cpus { cpus {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
@ -773,6 +780,63 @@ avb: ethernet@e6800000 {
status = "disabled"; status = "disabled";
}; };
can0: can@e6c30000 {
compatible = "renesas,can-r8a77990",
"renesas,rcar-gen3-can";
reg = <0 0xe6c30000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 916>,
<&cpg CPG_CORE R8A77990_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 916>;
status = "disabled";
};
can1: can@e6c38000 {
compatible = "renesas,can-r8a77990",
"renesas,rcar-gen3-can";
reg = <0 0xe6c38000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 915>,
<&cpg CPG_CORE R8A77990_CLK_CANFD>,
<&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 915>;
status = "disabled";
};
canfd: can@e66c0000 {
compatible = "renesas,r8a77990-canfd",
"renesas,rcar-gen3-canfd";
reg = <0 0xe66c0000 0 0x8000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 914>,
<&cpg CPG_CORE R8A77990_CLK_CANFD>,
<&can_clk>;
clock-names = "fck", "canfd", "can_clk";
assigned-clocks = <&cpg CPG_CORE R8A77990_CLK_CANFD>;
assigned-clock-rates = <40000000>;
power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
resets = <&cpg 914>;
status = "disabled";
channel0 {
status = "disabled";
};
channel1 {
status = "disabled";
};
};
pwm0: pwm@e6e30000 { pwm0: pwm@e6e30000 {
compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar"; compatible = "renesas,pwm-r8a77990", "renesas,pwm-rcar";
reg = <0 0xe6e30000 0 0x8>; reg = <0 0xe6e30000 0 0x8>;