AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-19 22:07:49 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

drm/i915/skl: Propagate the error if we fail to find a suitable DPLL divider

Browse Source 
At the moment, even if we fail to find a suitable divider, we'll still
try to set the mode with bogus parameters.

Just fail the modeset if we can't generate the frequency.

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Damien Lespiau 2015-05-07 18:38:40 +01:00 committed by Daniel Vetter
parent 19cdc0e6cd
commit 318bd821d6
1 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
drivers/gpu/drm/i915/intel_ddi.c
View File

@ -1115,7 +1115,7 @@ struct skl_wrpll_params {
uint32_t central_freq;
};
static void
static bool
skl_ddi_calculate_wrpll(int clock /* in Hz */,
struct skl_wrpll_params *wrpll_params)
{
@ -1196,6 +1196,7 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
if (min_dco_index > 2) {
WARN(1, "No valid parameters found for pixel clock: %dHz\n",
clock);
return false;
} else {
wrpll_params->central_freq = dco_central_freq[min_dco_index];
@ -1262,6 +1263,8 @@ skl_ddi_calculate_wrpll(int clock /* in Hz */,
wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1));
}
return true;
}
@ -1286,7 +1289,8 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params);
if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
return false;
cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |