AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-11-24 14:51:00 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity

clk: core: Force setting the phase delay when no change

Browse Source 
This patch reverts commit 023bd7166b ("clk: skip unnecessary
set_phase if nothing to do"), fixing two problems:

* in some SoCs, the hardware phase delay depends on the rate ratio of
  the clock and its parent. So, changing this ratio may imply to set
  new hardware values, even if the logical delay is the same.

* when the delay was the same as previously, an error was returned.

Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
Fixes: 023bd7166b ("clk: skip unnecessary set_phase if nothing to do")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Jean-Francois Moine 2016-08-24 08:32:51 +02:00 committed by Stephen Boyd
parent 911d49c7a0
commit 3174b0c9a6
1 changed files with 0 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
drivers/clk/clk.c
View File

@ -1908,10 +1908,6 @@ int clk_set_phase(struct clk *clk, int degrees)
clk_prepare_lock();
/* bail early if nothing to do */
if (degrees == clk->core->phase)
goto out;
trace_clk_set_phase(clk->core, degrees);
if (clk->core->ops->set_phase)
@ -1922,7 +1918,6 @@ int clk_set_phase(struct clk *clk, int degrees)
if (!ret)
clk->core->phase = degrees;
out:
clk_prepare_unlock();
return ret;