mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 09:56:40 +07:00
Merge branch 'omap-clock-for-next' of git://git.pwsan.com/linux-2.6 into devel
This commit is contained in:
Russell King
Russell King
commit
312cec5d09
@ -302,7 +302,7 @@ int omap2_wait_clock_ready(void __iomem *reg, u32 mask, const char *name)
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udelay(1);
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}
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if (i < MAX_CLOCK_ENABLE_WAIT)
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if (i <= MAX_CLOCK_ENABLE_WAIT)
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pr_debug("Clock %s stable after %d loops\n", name, i);
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else
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printk(KERN_ERR "Clock %s didn't enable in %d tries\n",
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@ -286,6 +286,20 @@ static struct omap_clk omap34xx_clks[] = {
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#define MIN_SDRC_DLL_LOCK_FREQ 83000000
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#define CYCLES_PER_MHZ 1000000
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/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
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#define SDRC_MPURATE_SCALE 8
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/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
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#define SDRC_MPURATE_BASE_SHIFT 9
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/*
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* SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
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* 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
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*/
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#define SDRC_MPURATE_LOOPS 96
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/**
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* omap3_dpll_recalc - recalculate DPLL rate
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* @clk: DPLL struct clk
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@ -709,7 +723,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 new_div = 0;
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u32 unlock_dll = 0;
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unsigned long validrate, sdrcrate;
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u32 c;
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unsigned long validrate, sdrcrate, mpurate;
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struct omap_sdrc_params *sp;
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if (!clk || !rate)
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@ -718,18 +733,15 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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if (clk != &dpll3_m2_ck)
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return -EINVAL;
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if (rate == clk->rate)
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return 0;
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validrate = omap2_clksel_round_rate_div(clk, rate, &new_div);
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if (validrate != rate)
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return -EINVAL;
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sdrcrate = sdrc_ick.rate;
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if (rate > clk->rate)
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sdrcrate <<= ((rate / clk->rate) - 1);
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sdrcrate <<= ((rate / clk->rate) >> 1);
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else
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sdrcrate >>= ((clk->rate / rate) - 1);
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sdrcrate >>= ((clk->rate / rate) >> 1);
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sp = omap2_sdrc_get_params(sdrcrate);
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if (!sp)
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@ -740,17 +752,25 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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unlock_dll = 1;
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}
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/*
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* XXX This only needs to be done when the CPU frequency changes
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*/
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mpurate = arm_fck.rate / CYCLES_PER_MHZ;
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c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
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c += 1; /* for safety */
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c *= SDRC_MPURATE_LOOPS;
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c >>= SDRC_MPURATE_SCALE;
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if (c == 0)
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c = 1;
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pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
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validrate);
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pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
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sp->rfr_ctrl, sp->actim_ctrla, sp->actim_ctrlb);
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/* REVISIT: SRAM code doesn't support other M2 divisors yet */
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WARN_ON(new_div != 1 && new_div != 2);
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/* REVISIT: Add SDRC_MR changing to this code also */
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omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
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sp->actim_ctrlb, new_div, unlock_dll);
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sp->actim_ctrlb, new_div, unlock_dll, c,
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sp->mr, rate > clk->rate);
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return 0;
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}
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@ -21,6 +21,7 @@
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <asm/tlb.h>
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@ -241,6 +242,40 @@ void __init omap2_map_common_io(void)
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omapfb_reserve_sdram();
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}
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/*
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* omap2_init_reprogram_sdrc - reprogram SDRC timing parameters
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*
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* Sets the CORE DPLL3 M2 divider to the same value that it's at
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* currently. This has the effect of setting the SDRC SDRAM AC timing
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* registers to the values currently defined by the kernel. Currently
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* only defined for OMAP3; will return 0 if called on OMAP2. Returns
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* -EINVAL if the dpll3_m2_ck cannot be found, 0 if called on OMAP2,
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* or passes along the return value of clk_set_rate().
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*/
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static int __init _omap2_init_reprogram_sdrc(void)
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{
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struct clk *dpll3_m2_ck;
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int v = -EINVAL;
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long rate;
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if (!cpu_is_omap34xx())
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return 0;
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dpll3_m2_ck = clk_get(NULL, "dpll3_m2_ck");
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if (!dpll3_m2_ck)
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return -EINVAL;
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rate = clk_get_rate(dpll3_m2_ck);
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pr_info("Reprogramming SDRC clock to %ld Hz\n", rate);
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v = clk_set_rate(dpll3_m2_ck, rate);
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if (v)
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pr_err("dpll3_m2_clk rate change failed: %d\n", v);
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clk_put(dpll3_m2_ck);
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return v;
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}
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void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
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{
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omap2_mux_init();
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@ -249,6 +284,7 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sp)
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clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
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omap2_clk_init();
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omap2_sdrc_init(sp);
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_omap2_init_reprogram_sdrc();
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#endif
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gpmc_init();
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}
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@ -1099,7 +1099,7 @@ int pwrdm_wait_transition(struct powerdomain *pwrdm)
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(c++ < PWRDM_TRANSITION_BAILOUT))
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udelay(1);
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if (c >= PWRDM_TRANSITION_BAILOUT) {
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if (c > PWRDM_TRANSITION_BAILOUT) {
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printk(KERN_ERR "powerdomain: waited too long for "
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"powerdomain %s to complete transition\n", pwrdm->name);
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return -EAGAIN;
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@ -3,13 +3,12 @@
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*
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* Omap3 specific functions that need to be run in internal SRAM
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*
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* (C) Copyright 2007
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* Texas Instruments Inc.
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* Rajendra Nayak <rnayak@ti.com>
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* Copyright (C) 2004, 2007, 2008 Texas Instruments, Inc.
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* Copyright (C) 2008 Nokia Corporation
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*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Rajendra Nayak <rnayak@ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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* Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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@ -37,61 +36,112 @@
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.text
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/* r4 parameters */
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#define SDRC_NO_UNLOCK_DLL 0x0
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#define SDRC_UNLOCK_DLL 0x1
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/* SDRC_DLLA_CTRL bit settings */
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#define FIXEDDELAY_SHIFT 24
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#define FIXEDDELAY_MASK (0xff << FIXEDDELAY_SHIFT)
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#define DLLIDLE_MASK 0x4
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/*
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* Change frequency of core dpll
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* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
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* r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
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* SDRC_DLLA_CTRL default values: TI hardware team indicates that
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* FIXEDDELAY should be initialized to 0xf. This apparently was
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* empirically determined during process testing, so no derivation
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* was provided.
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*/
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#define FIXEDDELAY_DEFAULT (0x0f << FIXEDDELAY_SHIFT)
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/* SDRC_DLLA_STATUS bit settings */
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#define LOCKSTATUS_MASK 0x4
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/* SDRC_POWER bit settings */
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#define SRFRONIDLEREQ_MASK 0x40
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#define PWDENA_MASK 0x4
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/* CM_IDLEST1_CORE bit settings */
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#define ST_SDRC_MASK 0x2
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/* CM_ICLKEN1_CORE bit settings */
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#define EN_SDRC_MASK 0x2
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/* CM_CLKSEL1_PLL bit settings */
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#define CORE_DPLL_CLKOUT_DIV_SHIFT 0x1b
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/*
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* omap3_sram_configure_core_dpll - change DPLL3 M2 divider
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* r0 = new SDRC_RFR_CTRL register contents
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* r1 = new SDRC_ACTIM_CTRLA register contents
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* r2 = new SDRC_ACTIM_CTRLB register contents
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* r3 = new M2 divider setting (only 1 and 2 supported right now)
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* r4 = unlock SDRC DLL? (1 = yes, 0 = no). Only unlock DLL for
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* SDRC rates < 83MHz
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* r5 = number of MPU cycles to wait for SDRC to stabilize after
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* reprogramming the SDRC when switching to a slower MPU speed
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* r6 = new SDRC_MR_0 register value
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* r7 = increasing SDRC rate? (1 = yes, 0 = no)
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*
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*/
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ENTRY(omap3_sram_configure_core_dpll)
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stmfd sp!, {r1-r12, lr} @ store regs to stack
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ldr r4, [sp, #52] @ pull extra args off the stack
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ldr r5, [sp, #56] @ load extra args from the stack
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ldr r6, [sp, #60] @ load extra args from the stack
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ldr r7, [sp, #64] @ load extra args from the stack
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dsb @ flush buffered writes to interconnect
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cmp r3, #0x2
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blne configure_sdrc
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cmp r4, #0x1
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cmp r7, #1 @ if increasing SDRC clk rate,
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bleq configure_sdrc @ program the SDRC regs early (for RFR)
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cmp r4, #SDRC_UNLOCK_DLL @ set the intended DLL state
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bleq unlock_dll
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blne lock_dll
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bl sdram_in_selfrefresh @ put the SDRAM in self refresh
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bl configure_core_dpll
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bl enable_sdrc
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cmp r4, #0x1
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bl sdram_in_selfrefresh @ put SDRAM in self refresh, idle SDRC
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bl configure_core_dpll @ change the DPLL3 M2 divider
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bl enable_sdrc @ take SDRC out of idle
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cmp r4, #SDRC_UNLOCK_DLL @ wait for DLL status to change
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bleq wait_dll_unlock
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blne wait_dll_lock
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cmp r3, #0x1
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blne configure_sdrc
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cmp r7, #1 @ if increasing SDRC clk rate,
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beq return_to_sdram @ return to SDRAM code, otherwise,
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bl configure_sdrc @ reprogram SDRC regs now
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mov r12, r5
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bl wait_clk_stable @ wait for SDRC to stabilize
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return_to_sdram:
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isb @ prevent speculative exec past here
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mov r0, #0 @ return value
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ldmfd sp!, {r1-r12, pc} @ restore regs and return
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unlock_dll:
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ldr r11, omap3_sdrc_dlla_ctrl
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ldr r12, [r11]
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orr r12, r12, #0x4
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and r12, r12, #FIXEDDELAY_MASK
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orr r12, r12, #FIXEDDELAY_DEFAULT
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orr r12, r12, #DLLIDLE_MASK
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str r12, [r11] @ (no OCP barrier needed)
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bx lr
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lock_dll:
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ldr r11, omap3_sdrc_dlla_ctrl
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ldr r12, [r11]
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bic r12, r12, #0x4
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bic r12, r12, #DLLIDLE_MASK
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str r12, [r11] @ (no OCP barrier needed)
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bx lr
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sdram_in_selfrefresh:
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ldr r11, omap3_sdrc_power @ read the SDRC_POWER register
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ldr r12, [r11] @ read the contents of SDRC_POWER
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mov r9, r12 @ keep a copy of SDRC_POWER bits
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orr r12, r12, #0x40 @ enable self refresh on idle req
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bic r12, r12, #0x4 @ clear PWDENA
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orr r12, r12, #SRFRONIDLEREQ_MASK @ enable self refresh on idle
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bic r12, r12, #PWDENA_MASK @ clear PWDENA
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str r12, [r11] @ write back to SDRC_POWER register
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ldr r12, [r11] @ posted-write barrier for SDRC
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idle_sdrc:
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ldr r11, omap3_cm_iclken1_core @ read the CM_ICLKEN1_CORE reg
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ldr r12, [r11]
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bic r12, r12, #0x2 @ disable iclk bit for SDRC
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bic r12, r12, #EN_SDRC_MASK @ disable iclk bit for SDRC
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str r12, [r11]
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wait_sdrc_idle:
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ldr r11, omap3_cm_idlest1_core
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ldr r12, [r11]
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and r12, r12, #0x2 @ check for SDRC idle
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cmp r12, #2
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and r12, r12, #ST_SDRC_MASK @ check for SDRC idle
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cmp r12, #ST_SDRC_MASK
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bne wait_sdrc_idle
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bx lr
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configure_core_dpll:
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@ -99,36 +149,23 @@ configure_core_dpll:
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ldr r12, [r11]
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ldr r10, core_m2_mask_val @ modify m2 for core dpll
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and r12, r12, r10
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orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
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orr r12, r12, r3, lsl #CORE_DPLL_CLKOUT_DIV_SHIFT
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str r12, [r11]
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ldr r12, [r11] @ posted-write barrier for CM
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mov r12, #0x800 @ wait for the clock to stabilise
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cmp r3, #2
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bne wait_clk_stable
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bx lr
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wait_clk_stable:
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subs r12, r12, #1
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bne wait_clk_stable
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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bx lr
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enable_sdrc:
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ldr r11, omap3_cm_iclken1_core
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ldr r12, [r11]
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orr r12, r12, #0x2 @ enable iclk bit for SDRC
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orr r12, r12, #EN_SDRC_MASK @ enable iclk bit for SDRC
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str r12, [r11]
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wait_sdrc_idle1:
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ldr r11, omap3_cm_idlest1_core
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ldr r12, [r11]
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and r12, r12, #0x2
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and r12, r12, #ST_SDRC_MASK
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cmp r12, #0
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bne wait_sdrc_idle1
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restore_sdrc_power_val:
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@ -138,14 +175,14 @@ restore_sdrc_power_val:
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wait_dll_lock:
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ldr r11, omap3_sdrc_dlla_status
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ldr r12, [r11]
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and r12, r12, #0x4
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cmp r12, #0x4
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and r12, r12, #LOCKSTATUS_MASK
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cmp r12, #LOCKSTATUS_MASK
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bne wait_dll_lock
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bx lr
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wait_dll_unlock:
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ldr r11, omap3_sdrc_dlla_status
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ldr r12, [r11]
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and r12, r12, #0x4
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and r12, r12, #LOCKSTATUS_MASK
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cmp r12, #0x0
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bne wait_dll_unlock
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bx lr
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@ -156,7 +193,9 @@ configure_sdrc:
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str r1, [r11]
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ldr r11, omap3_sdrc_actim_ctrlb
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str r2, [r11]
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ldr r2, [r11] @ posted-write barrier for SDRC
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ldr r11, omap3_sdrc_mr_0
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str r6, [r11]
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ldr r6, [r11] @ posted-write barrier for SDRC
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bx lr
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omap3_sdrc_power:
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@ -173,6 +212,8 @@ omap3_sdrc_actim_ctrla:
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.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_A_0)
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omap3_sdrc_actim_ctrlb:
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.word OMAP34XX_SDRC_REGADDR(SDRC_ACTIM_CTRL_B_0)
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omap3_sdrc_mr_0:
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.word OMAP34XX_SDRC_REGADDR(SDRC_MR_0)
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omap3_sdrc_dlla_status:
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.word OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
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omap3_sdrc_dlla_ctrl:
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@ -24,7 +24,8 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
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extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
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u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb, u32 m2,
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u32 unlock_dll);
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u32 unlock_dll, u32 f, u32 sdrc_mr,
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u32 inc);
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/* Do not use these */
|
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extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
|
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@ -62,7 +63,8 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
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extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
|
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u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb, u32 m2,
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u32 unlock_dll);
|
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u32 unlock_dll, u32 f, u32 sdrc_mr,
|
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u32 inc);
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extern unsigned long omap3_sram_configure_core_dpll_sz;
|
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||||
#endif
|
||||
|
||||
@ -371,15 +371,17 @@ static inline int omap243x_sram_init(void)
|
||||
static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
|
||||
u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb,
|
||||
u32 m2, u32 unlock_dll);
|
||||
u32 m2, u32 unlock_dll,
|
||||
u32 f, u32 sdrc_mr, u32 inc);
|
||||
u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
|
||||
u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll)
|
||||
u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
|
||||
u32 f, u32 sdrc_mr, u32 inc)
|
||||
{
|
||||
BUG_ON(!_omap3_sram_configure_core_dpll);
|
||||
return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
|
||||
sdrc_actim_ctrla,
|
||||
sdrc_actim_ctrlb, m2,
|
||||
unlock_dll);
|
||||
unlock_dll, f, sdrc_mr, inc);
|
||||
}
|
||||
|
||||
/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user