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drm/amdgpu/soc15: initialize reg base for vega12

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Initialize the IP offsets for vega12.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Hawking Zhang 2018-03-12 18:25:15 +08:00 committed by Alex Deucher
parent f559fe2bc1
commit 3084eb0011
1 changed files with 1 additions and 0 deletions
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drivers/gpu/drm/amd/amdgpu/soc15.c
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@ -508,6 +508,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
/* Set IP register base before any HW register access */ /* Set IP register base before any HW register access */
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_VEGA10: case CHIP_VEGA10:
case CHIP_VEGA12:
case CHIP_RAVEN: case CHIP_RAVEN:
vega10_reg_base_init(adev); vega10_reg_base_init(adev);
break; break;