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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-02 19:56:43 +07:00
drm/radeon/kms: skip db/cb/streamout checking when possible on evergreen
Signed-off-by: Marek Olšák <maraeo@gmail.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Marek Olšák
Dave Airlie
parent
7e9fa5f69f
commit
308385782d
@ -86,6 +86,9 @@ struct evergreen_cs_track {
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struct radeon_bo *db_s_read_bo;
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struct radeon_bo *db_s_write_bo;
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bool sx_misc_kill_all_prims;
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bool cb_dirty;
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bool db_dirty;
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bool streamout_dirty;
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};
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static u32 evergreen_cs_get_aray_mode(u32 tiling_flags)
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@ -139,6 +142,7 @@ static void evergreen_cs_track_init(struct evergreen_cs_track *track)
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}
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track->cb_target_mask = 0xFFFFFFFF;
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track->cb_shader_mask = 0xFFFFFFFF;
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track->cb_dirty = true;
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track->db_depth_view = 0xFFFFC000;
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track->db_depth_size = 0xFFFFFFFF;
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@ -156,6 +160,7 @@ static void evergreen_cs_track_init(struct evergreen_cs_track *track)
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track->db_s_write_offset = 0xFFFFFFFF;
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track->db_s_read_bo = NULL;
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track->db_s_write_bo = NULL;
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track->db_dirty = true;
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for (i = 0; i < 4; i++) {
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track->vgt_strmout_size[i] = 0;
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@ -163,6 +168,7 @@ static void evergreen_cs_track_init(struct evergreen_cs_track *track)
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track->vgt_strmout_bo_offset[i] = 0xFFFFFFFF;
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track->vgt_strmout_bo_mc[i] = 0xFFFFFFFF;
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}
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track->streamout_dirty = true;
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track->sx_misc_kill_all_prims = false;
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}
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@ -802,7 +808,7 @@ static int evergreen_cs_track_check(struct radeon_cs_parser *p)
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unsigned buffer_mask = 0;
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/* check streamout */
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if (track->vgt_strmout_config) {
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if (track->streamout_dirty && track->vgt_strmout_config) {
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for (i = 0; i < 4; i++) {
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if (track->vgt_strmout_config & (1 << i)) {
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buffer_mask |= (track->vgt_strmout_buffer_config >> (i * 4)) & 0xf;
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@ -826,6 +832,7 @@ static int evergreen_cs_track_check(struct radeon_cs_parser *p)
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}
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}
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}
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track->streamout_dirty = false;
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}
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if (track->sx_misc_kill_all_prims)
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@ -833,34 +840,40 @@ static int evergreen_cs_track_check(struct radeon_cs_parser *p)
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/* check that we have a cb for each enabled target
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*/
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tmp = track->cb_target_mask;
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for (i = 0; i < 8; i++) {
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if ((tmp >> (i * 4)) & 0xF) {
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/* at least one component is enabled */
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if (track->cb_color_bo[i] == NULL) {
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dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
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__func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
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return -EINVAL;
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}
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/* check cb */
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r = evergreen_cs_track_validate_cb(p, i);
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if (r) {
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return r;
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if (track->cb_dirty) {
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tmp = track->cb_target_mask;
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for (i = 0; i < 8; i++) {
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if ((tmp >> (i * 4)) & 0xF) {
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/* at least one component is enabled */
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if (track->cb_color_bo[i] == NULL) {
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dev_warn(p->dev, "%s:%d mask 0x%08X | 0x%08X no cb for %d\n",
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__func__, __LINE__, track->cb_target_mask, track->cb_shader_mask, i);
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return -EINVAL;
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}
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/* check cb */
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r = evergreen_cs_track_validate_cb(p, i);
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if (r) {
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return r;
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}
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}
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}
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track->cb_dirty = false;
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}
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/* Check stencil buffer */
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if (G_028800_STENCIL_ENABLE(track->db_depth_control)) {
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r = evergreen_cs_track_validate_stencil(p);
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if (r)
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return r;
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}
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/* Check depth buffer */
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if (G_028800_Z_WRITE_ENABLE(track->db_depth_control)) {
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r = evergreen_cs_track_validate_depth(p);
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if (r)
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return r;
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if (track->db_dirty) {
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/* Check stencil buffer */
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if (G_028800_STENCIL_ENABLE(track->db_depth_control)) {
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r = evergreen_cs_track_validate_stencil(p);
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if (r)
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return r;
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}
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/* Check depth buffer */
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if (G_028800_Z_WRITE_ENABLE(track->db_depth_control)) {
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r = evergreen_cs_track_validate_depth(p);
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if (r)
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return r;
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}
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track->db_dirty = false;
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}
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return 0;
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@ -1194,6 +1207,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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break;
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case DB_DEPTH_CONTROL:
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track->db_depth_control = radeon_get_ib_value(p, idx);
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track->db_dirty = true;
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break;
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case CAYMAN_DB_EQAA:
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if (p->rdev->family < CHIP_CAYMAN) {
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@ -1235,19 +1249,24 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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DB_MACRO_TILE_ASPECT(mtaspect);
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}
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}
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track->db_dirty = true;
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break;
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case DB_STENCIL_INFO:
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track->db_s_info = radeon_get_ib_value(p, idx);
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track->db_dirty = true;
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break;
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case DB_DEPTH_VIEW:
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track->db_depth_view = radeon_get_ib_value(p, idx);
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track->db_dirty = true;
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break;
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case DB_DEPTH_SIZE:
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track->db_depth_size = radeon_get_ib_value(p, idx);
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track->db_depth_size_idx = idx;
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track->db_dirty = true;
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break;
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case R_02805C_DB_DEPTH_SLICE:
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track->db_depth_slice = radeon_get_ib_value(p, idx);
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track->db_dirty = true;
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break;
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case DB_Z_READ_BASE:
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r = evergreen_cs_packet_next_reloc(p, &reloc);
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@ -1259,6 +1278,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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track->db_z_read_offset = radeon_get_ib_value(p, idx);
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ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
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track->db_z_read_bo = reloc->robj;
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track->db_dirty = true;
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break;
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case DB_Z_WRITE_BASE:
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r = evergreen_cs_packet_next_reloc(p, &reloc);
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@ -1270,6 +1290,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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track->db_z_write_offset = radeon_get_ib_value(p, idx);
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ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
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track->db_z_write_bo = reloc->robj;
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track->db_dirty = true;
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break;
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case DB_STENCIL_READ_BASE:
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r = evergreen_cs_packet_next_reloc(p, &reloc);
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@ -1281,6 +1302,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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track->db_s_read_offset = radeon_get_ib_value(p, idx);
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ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
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track->db_s_read_bo = reloc->robj;
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track->db_dirty = true;
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break;
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case DB_STENCIL_WRITE_BASE:
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r = evergreen_cs_packet_next_reloc(p, &reloc);
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@ -1292,12 +1314,15 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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track->db_s_write_offset = radeon_get_ib_value(p, idx);
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ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
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track->db_s_write_bo = reloc->robj;
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track->db_dirty = true;
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break;
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case VGT_STRMOUT_CONFIG:
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track->vgt_strmout_config = radeon_get_ib_value(p, idx);
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track->streamout_dirty = true;
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break;
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case VGT_STRMOUT_BUFFER_CONFIG:
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track->vgt_strmout_buffer_config = radeon_get_ib_value(p, idx);
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track->streamout_dirty = true;
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break;
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case VGT_STRMOUT_BUFFER_BASE_0:
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case VGT_STRMOUT_BUFFER_BASE_1:
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@ -1314,6 +1339,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
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track->vgt_strmout_bo[tmp] = reloc->robj;
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track->vgt_strmout_bo_mc[tmp] = reloc->lobj.gpu_offset;
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track->streamout_dirty = true;
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break;
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case VGT_STRMOUT_BUFFER_SIZE_0:
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case VGT_STRMOUT_BUFFER_SIZE_1:
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@ -1322,6 +1348,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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tmp = (reg - VGT_STRMOUT_BUFFER_SIZE_0) / 16;
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/* size in register is DWs, convert to bytes */
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track->vgt_strmout_size[tmp] = radeon_get_ib_value(p, idx) * 4;
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track->streamout_dirty = true;
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break;
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case CP_COHER_BASE:
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r = evergreen_cs_packet_next_reloc(p, &reloc);
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@ -1333,9 +1360,11 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
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case CB_TARGET_MASK:
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track->cb_target_mask = radeon_get_ib_value(p, idx);
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track->cb_dirty = true;
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break;
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case CB_SHADER_MASK:
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track->cb_shader_mask = radeon_get_ib_value(p, idx);
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track->cb_dirty = true;
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break;
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case PA_SC_AA_CONFIG:
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if (p->rdev->family >= CHIP_CAYMAN) {
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@ -1365,6 +1394,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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case CB_COLOR7_VIEW:
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tmp = (reg - CB_COLOR0_VIEW) / 0x3c;
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track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
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track->cb_dirty = true;
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break;
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case CB_COLOR8_VIEW:
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case CB_COLOR9_VIEW:
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@ -1372,6 +1402,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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case CB_COLOR11_VIEW:
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tmp = ((reg - CB_COLOR8_VIEW) / 0x1c) + 8;
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track->cb_color_view[tmp] = radeon_get_ib_value(p, idx);
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track->cb_dirty = true;
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break;
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case CB_COLOR0_INFO:
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case CB_COLOR1_INFO:
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@ -1393,6 +1424,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
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track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
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}
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track->cb_dirty = true;
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break;
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case CB_COLOR8_INFO:
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case CB_COLOR9_INFO:
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@ -1410,6 +1442,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
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track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags));
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}
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track->cb_dirty = true;
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break;
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case CB_COLOR0_PITCH:
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case CB_COLOR1_PITCH:
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@ -1422,6 +1455,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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tmp = (reg - CB_COLOR0_PITCH) / 0x3c;
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track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
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track->cb_color_pitch_idx[tmp] = idx;
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track->cb_dirty = true;
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break;
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case CB_COLOR8_PITCH:
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case CB_COLOR9_PITCH:
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@ -1430,6 +1464,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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tmp = ((reg - CB_COLOR8_PITCH) / 0x1c) + 8;
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track->cb_color_pitch[tmp] = radeon_get_ib_value(p, idx);
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track->cb_color_pitch_idx[tmp] = idx;
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track->cb_dirty = true;
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break;
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case CB_COLOR0_SLICE:
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case CB_COLOR1_SLICE:
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@ -1442,6 +1477,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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tmp = (reg - CB_COLOR0_SLICE) / 0x3c;
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track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
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track->cb_color_slice_idx[tmp] = idx;
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track->cb_dirty = true;
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break;
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case CB_COLOR8_SLICE:
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case CB_COLOR9_SLICE:
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@ -1450,6 +1486,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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tmp = ((reg - CB_COLOR8_SLICE) / 0x1c) + 8;
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track->cb_color_slice[tmp] = radeon_get_ib_value(p, idx);
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track->cb_color_slice_idx[tmp] = idx;
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track->cb_dirty = true;
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break;
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case CB_COLOR0_ATTRIB:
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case CB_COLOR1_ATTRIB:
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@ -1481,6 +1518,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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}
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tmp = ((reg - CB_COLOR0_ATTRIB) / 0x3c);
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track->cb_color_attrib[tmp] = ib[idx];
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track->cb_dirty = true;
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break;
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case CB_COLOR8_ATTRIB:
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case CB_COLOR9_ATTRIB:
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@ -1508,6 +1546,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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}
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tmp = ((reg - CB_COLOR8_ATTRIB) / 0x1c) + 8;
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track->cb_color_attrib[tmp] = ib[idx];
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track->cb_dirty = true;
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break;
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case CB_COLOR0_DIM:
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case CB_COLOR1_DIM:
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@ -1604,6 +1643,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
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track->cb_color_base_last[tmp] = ib[idx];
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track->cb_color_bo[tmp] = reloc->robj;
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track->cb_dirty = true;
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break;
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case CB_COLOR8_BASE:
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case CB_COLOR9_BASE:
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@ -1620,6 +1660,7 @@ static int evergreen_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
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ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
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track->cb_color_base_last[tmp] = ib[idx];
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track->cb_color_bo[tmp] = reloc->robj;
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track->cb_dirty = true;
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break;
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case CB_IMMED0_BASE:
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case CB_IMMED1_BASE:
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