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efi: Parse ARM error information value
ARM errors just print out the error information value, then the value needs to be manually decoded as per the UEFI spec. Add decoding of the ARM error information value so that the kernel logs capture all of the valid information at first glance. ARM error information value decoding is captured in UEFI 2.7 spec tables 263-265. Signed-off-by: Tyler Baicar <tbaicar@codeaurora.org> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Arvind Yadav <arvind.yadav.cs@gmail.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Matt Fleming <matt@codeblueprint.co.uk> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vasyl Gomonovych <gomonovych@gmail.com> Cc: linux-efi@vger.kernel.org Link: http://lkml.kernel.org/r/20180102181042.19074-6-ard.biesheuvel@linaro.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
Tyler Baicar
Ingo Molnar
parent
c6d8c8ef1d
commit
301f55b1a9
@ -44,13 +44,218 @@ static const char * const arm_reg_ctx_strs[] = {
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"Misc. system register structure",
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};
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static const char * const arm_err_trans_type_strs[] = {
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"Instruction",
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"Data Access",
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"Generic",
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};
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static const char * const arm_bus_err_op_strs[] = {
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"Generic error (type cannot be determined)",
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"Generic read (type of instruction or data request cannot be determined)",
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"Generic write (type of instruction of data request cannot be determined)",
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"Data read",
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"Data write",
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"Instruction fetch",
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"Prefetch",
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};
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static const char * const arm_cache_err_op_strs[] = {
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"Generic error (type cannot be determined)",
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"Generic read (type of instruction or data request cannot be determined)",
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"Generic write (type of instruction of data request cannot be determined)",
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"Data read",
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"Data write",
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"Instruction fetch",
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"Prefetch",
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"Eviction",
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"Snooping (processor initiated a cache snoop that resulted in an error)",
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"Snooped (processor raised a cache error caused by another processor or device snooping its cache)",
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"Management",
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};
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static const char * const arm_tlb_err_op_strs[] = {
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"Generic error (type cannot be determined)",
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"Generic read (type of instruction or data request cannot be determined)",
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"Generic write (type of instruction of data request cannot be determined)",
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"Data read",
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"Data write",
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"Instruction fetch",
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"Prefetch",
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"Local management operation (processor initiated a TLB management operation that resulted in an error)",
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"External management operation (processor raised a TLB error caused by another processor or device broadcasting TLB operations)",
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};
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static const char * const arm_bus_err_part_type_strs[] = {
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"Local processor originated request",
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"Local processor responded to request",
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"Local processor observed",
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"Generic",
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};
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static const char * const arm_bus_err_addr_space_strs[] = {
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"External Memory Access",
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"Internal Memory Access",
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"Unknown",
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"Device Memory Access",
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};
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static void cper_print_arm_err_info(const char *pfx, u32 type,
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u64 error_info)
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{
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u8 trans_type, op_type, level, participation_type, address_space;
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u16 mem_attributes;
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bool proc_context_corrupt, corrected, precise_pc, restartable_pc;
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bool time_out, access_mode;
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/* If the type is unknown, bail. */
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if (type > CPER_ARM_MAX_TYPE)
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return;
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/*
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* Vendor type errors have error information values that are vendor
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* specific.
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*/
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if (type == CPER_ARM_VENDOR_ERROR)
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return;
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if (error_info & CPER_ARM_ERR_VALID_TRANSACTION_TYPE) {
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trans_type = ((error_info >> CPER_ARM_ERR_TRANSACTION_SHIFT)
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& CPER_ARM_ERR_TRANSACTION_MASK);
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if (trans_type < ARRAY_SIZE(arm_err_trans_type_strs)) {
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printk("%stransaction type: %s\n", pfx,
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arm_err_trans_type_strs[trans_type]);
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}
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}
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if (error_info & CPER_ARM_ERR_VALID_OPERATION_TYPE) {
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op_type = ((error_info >> CPER_ARM_ERR_OPERATION_SHIFT)
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& CPER_ARM_ERR_OPERATION_MASK);
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switch (type) {
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case CPER_ARM_CACHE_ERROR:
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if (op_type < ARRAY_SIZE(arm_cache_err_op_strs)) {
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printk("%soperation type: %s\n", pfx,
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arm_cache_err_op_strs[op_type]);
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}
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break;
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case CPER_ARM_TLB_ERROR:
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if (op_type < ARRAY_SIZE(arm_tlb_err_op_strs)) {
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printk("%soperation type: %s\n", pfx,
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arm_tlb_err_op_strs[op_type]);
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}
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break;
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case CPER_ARM_BUS_ERROR:
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if (op_type < ARRAY_SIZE(arm_bus_err_op_strs)) {
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printk("%soperation type: %s\n", pfx,
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arm_bus_err_op_strs[op_type]);
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}
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break;
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}
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}
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if (error_info & CPER_ARM_ERR_VALID_LEVEL) {
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level = ((error_info >> CPER_ARM_ERR_LEVEL_SHIFT)
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& CPER_ARM_ERR_LEVEL_MASK);
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switch (type) {
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case CPER_ARM_CACHE_ERROR:
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printk("%scache level: %d\n", pfx, level);
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break;
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case CPER_ARM_TLB_ERROR:
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printk("%sTLB level: %d\n", pfx, level);
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break;
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case CPER_ARM_BUS_ERROR:
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printk("%saffinity level at which the bus error occurred: %d\n",
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pfx, level);
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break;
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}
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}
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if (error_info & CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT) {
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proc_context_corrupt = ((error_info >> CPER_ARM_ERR_PC_CORRUPT_SHIFT)
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& CPER_ARM_ERR_PC_CORRUPT_MASK);
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if (proc_context_corrupt)
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printk("%sprocessor context corrupted\n", pfx);
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else
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printk("%sprocessor context not corrupted\n", pfx);
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}
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if (error_info & CPER_ARM_ERR_VALID_CORRECTED) {
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corrected = ((error_info >> CPER_ARM_ERR_CORRECTED_SHIFT)
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& CPER_ARM_ERR_CORRECTED_MASK);
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if (corrected)
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printk("%sthe error has been corrected\n", pfx);
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else
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printk("%sthe error has not been corrected\n", pfx);
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}
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if (error_info & CPER_ARM_ERR_VALID_PRECISE_PC) {
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precise_pc = ((error_info >> CPER_ARM_ERR_PRECISE_PC_SHIFT)
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& CPER_ARM_ERR_PRECISE_PC_MASK);
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if (precise_pc)
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printk("%sPC is precise\n", pfx);
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else
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printk("%sPC is imprecise\n", pfx);
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}
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if (error_info & CPER_ARM_ERR_VALID_RESTARTABLE_PC) {
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restartable_pc = ((error_info >> CPER_ARM_ERR_RESTARTABLE_PC_SHIFT)
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& CPER_ARM_ERR_RESTARTABLE_PC_MASK);
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if (restartable_pc)
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printk("%sProgram execution can be restarted reliably at the PC associated with the error.\n", pfx);
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}
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/* The rest of the fields are specific to bus errors */
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if (type != CPER_ARM_BUS_ERROR)
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return;
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if (error_info & CPER_ARM_ERR_VALID_PARTICIPATION_TYPE) {
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participation_type = ((error_info >> CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT)
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& CPER_ARM_ERR_PARTICIPATION_TYPE_MASK);
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if (participation_type < ARRAY_SIZE(arm_bus_err_part_type_strs)) {
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printk("%sparticipation type: %s\n", pfx,
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arm_bus_err_part_type_strs[participation_type]);
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}
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}
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if (error_info & CPER_ARM_ERR_VALID_TIME_OUT) {
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time_out = ((error_info >> CPER_ARM_ERR_TIME_OUT_SHIFT)
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& CPER_ARM_ERR_TIME_OUT_MASK);
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if (time_out)
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printk("%srequest timed out\n", pfx);
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}
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if (error_info & CPER_ARM_ERR_VALID_ADDRESS_SPACE) {
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address_space = ((error_info >> CPER_ARM_ERR_ADDRESS_SPACE_SHIFT)
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& CPER_ARM_ERR_ADDRESS_SPACE_MASK);
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if (address_space < ARRAY_SIZE(arm_bus_err_addr_space_strs)) {
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printk("%saddress space: %s\n", pfx,
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arm_bus_err_addr_space_strs[address_space]);
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}
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}
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if (error_info & CPER_ARM_ERR_VALID_MEM_ATTRIBUTES) {
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mem_attributes = ((error_info >> CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT)
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& CPER_ARM_ERR_MEM_ATTRIBUTES_MASK);
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printk("%smemory access attributes:0x%x\n", pfx, mem_attributes);
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}
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if (error_info & CPER_ARM_ERR_VALID_ACCESS_MODE) {
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access_mode = ((error_info >> CPER_ARM_ERR_ACCESS_MODE_SHIFT)
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& CPER_ARM_ERR_ACCESS_MODE_MASK);
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if (access_mode)
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printk("%saccess mode: normal\n", pfx);
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else
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printk("%saccess mode: secure\n", pfx);
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}
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}
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void cper_print_proc_arm(const char *pfx,
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const struct cper_sec_proc_arm *proc)
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{
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int i, len, max_ctx_type;
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struct cper_arm_err_info *err_info;
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struct cper_arm_ctx_info *ctx_info;
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char newpfx[64];
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char newpfx[64], infopfx[64];
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printk("%sMIDR: 0x%016llx\n", pfx, proc->midr);
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@ -102,9 +307,13 @@ void cper_print_proc_arm(const char *pfx,
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printk("%serror_type: %d, %s\n", newpfx, err_info->type,
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err_info->type < ARRAY_SIZE(cper_proc_error_type_strs) ?
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cper_proc_error_type_strs[err_info->type] : "unknown");
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if (err_info->validation_bits & CPER_ARM_INFO_VALID_ERR_INFO)
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if (err_info->validation_bits & CPER_ARM_INFO_VALID_ERR_INFO) {
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printk("%serror_info: 0x%016llx\n", newpfx,
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err_info->error_info);
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snprintf(infopfx, sizeof(infopfx), "%s%s", newpfx, INDENT_SP);
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cper_print_arm_err_info(infopfx, err_info->type,
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err_info->error_info);
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}
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if (err_info->validation_bits & CPER_ARM_INFO_VALID_VIRT_ADDR)
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printk("%svirtual fault address: 0x%016llx\n",
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newpfx, err_info->virt_fault_addr);
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@ -275,6 +275,50 @@ enum {
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#define CPER_ARM_INFO_FLAGS_PROPAGATED BIT(2)
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#define CPER_ARM_INFO_FLAGS_OVERFLOW BIT(3)
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#define CPER_ARM_CACHE_ERROR 0
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#define CPER_ARM_TLB_ERROR 1
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#define CPER_ARM_BUS_ERROR 2
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#define CPER_ARM_VENDOR_ERROR 3
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#define CPER_ARM_MAX_TYPE CPER_ARM_VENDOR_ERROR
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#define CPER_ARM_ERR_VALID_TRANSACTION_TYPE BIT(0)
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#define CPER_ARM_ERR_VALID_OPERATION_TYPE BIT(1)
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#define CPER_ARM_ERR_VALID_LEVEL BIT(2)
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#define CPER_ARM_ERR_VALID_PROC_CONTEXT_CORRUPT BIT(3)
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#define CPER_ARM_ERR_VALID_CORRECTED BIT(4)
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#define CPER_ARM_ERR_VALID_PRECISE_PC BIT(5)
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#define CPER_ARM_ERR_VALID_RESTARTABLE_PC BIT(6)
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#define CPER_ARM_ERR_VALID_PARTICIPATION_TYPE BIT(7)
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#define CPER_ARM_ERR_VALID_TIME_OUT BIT(8)
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#define CPER_ARM_ERR_VALID_ADDRESS_SPACE BIT(9)
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#define CPER_ARM_ERR_VALID_MEM_ATTRIBUTES BIT(10)
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#define CPER_ARM_ERR_VALID_ACCESS_MODE BIT(11)
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#define CPER_ARM_ERR_TRANSACTION_SHIFT 16
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#define CPER_ARM_ERR_TRANSACTION_MASK GENMASK(1,0)
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#define CPER_ARM_ERR_OPERATION_SHIFT 18
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#define CPER_ARM_ERR_OPERATION_MASK GENMASK(3,0)
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#define CPER_ARM_ERR_LEVEL_SHIFT 22
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#define CPER_ARM_ERR_LEVEL_MASK GENMASK(2,0)
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#define CPER_ARM_ERR_PC_CORRUPT_SHIFT 25
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#define CPER_ARM_ERR_PC_CORRUPT_MASK GENMASK(0,0)
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#define CPER_ARM_ERR_CORRECTED_SHIFT 26
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#define CPER_ARM_ERR_CORRECTED_MASK GENMASK(0,0)
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#define CPER_ARM_ERR_PRECISE_PC_SHIFT 27
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#define CPER_ARM_ERR_PRECISE_PC_MASK GENMASK(0,0)
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#define CPER_ARM_ERR_RESTARTABLE_PC_SHIFT 28
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#define CPER_ARM_ERR_RESTARTABLE_PC_MASK GENMASK(0,0)
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#define CPER_ARM_ERR_PARTICIPATION_TYPE_SHIFT 29
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#define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK GENMASK(1,0)
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#define CPER_ARM_ERR_TIME_OUT_SHIFT 31
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#define CPER_ARM_ERR_TIME_OUT_MASK GENMASK(0,0)
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#define CPER_ARM_ERR_ADDRESS_SPACE_SHIFT 32
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#define CPER_ARM_ERR_ADDRESS_SPACE_MASK GENMASK(1,0)
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#define CPER_ARM_ERR_MEM_ATTRIBUTES_SHIFT 34
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#define CPER_ARM_ERR_MEM_ATTRIBUTES_MASK GENMASK(8,0)
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#define CPER_ARM_ERR_ACCESS_MODE_SHIFT 43
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#define CPER_ARM_ERR_ACCESS_MODE_MASK GENMASK(0,0)
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/*
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* All tables and structs must be byte-packed to match CPER
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* specification, since the tables are provided by the system BIOS
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