mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 22:46:48 +07:00
serial: mvebu-uart: clear state register before IRQ request
When receiving data on RX pin before ->uart_startup() is called, some error bits in the state register could be set up (like BRK_DET). This is harmless when using only the standard UART (error bits are read-only), but may procude an endless loop once in the extended UART RX interrupt handler (error bits must be cleared). Clear the status register in ->uart_startup() to avoid this situation. Signed-off-by: Allen Yan <yanwei@marvell.com> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
68a0db1d7d
commit
2ff23c4802
@ -322,6 +322,12 @@ static int mvebu_uart_startup(struct uart_port *port)
|
||||
writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
|
||||
port->membase + UART_CTRL(port));
|
||||
udelay(1);
|
||||
|
||||
/* Clear the error bits of state register before IRQ request */
|
||||
ret = readl(port->membase + UART_STAT);
|
||||
ret |= STAT_BRK_ERR;
|
||||
writel(ret, port->membase + UART_STAT);
|
||||
|
||||
writel(CTRL_BRK_INT, port->membase + UART_CTRL(port));
|
||||
|
||||
ctl = readl(port->membase + UART_INTR(port));
|
||||
|
Loading…
Reference in New Issue
Block a user