mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-29 22:26:44 +07:00
Merge master.kernel.org:/pub/scm/linux/kernel/git/bart/ide-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/bart/ide-2.6: ide: remove CONFIG_IDEDMA_{ICS,PCI}_AUTO config options ide: don't allow DMA to be enabled if CONFIG_IDEDMA_{ICS,PCI}_AUTO=n scc_pata: dependency fix jmicron: make ide jmicron driver play nice with libata ones ide: remove static prototypes from include/asm-mips/mach-au1x00/au1xxx_ide.h ide: au1xxx: fix use of mixed declarations and code cmd64x: fix recovery time calculation (take 3)
This commit is contained in:
commit
2f8dd8505e
@ -434,24 +434,8 @@ config BLK_DEV_IDEDMA_FORCED
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Generally say N here.
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config IDEDMA_PCI_AUTO
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bool "Use PCI DMA by default when available"
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---help---
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Prior to kernel version 2.1.112, Linux used to automatically use
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DMA for IDE drives and chipsets which support it. Due to concerns
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about a couple of cases where buggy hardware may have caused damage,
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the default is now to NOT use DMA automatically. To revert to the
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previous behaviour, say Y to this question.
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If you suspect your hardware is at all flakey, say N here.
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Do NOT email the IDE kernel people regarding this issue!
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It is normally safe to answer Y to this question unless your
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motherboard uses a VIA VP2 chipset, in which case you should say N.
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config IDEDMA_ONLYDISK
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bool "Enable DMA only for disks "
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depends on IDEDMA_PCI_AUTO
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help
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This is used if you know your ATAPI Devices are going to fail DMA
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Transfers.
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@ -769,6 +753,14 @@ config BLK_DEV_TC86C001
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help
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This driver adds support for Toshiba TC86C001 GOKU-S chip.
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config BLK_DEV_CELLEB
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tristate "Toshiba's Cell Reference Set IDE support"
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depends on PPC_CELLEB
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help
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This driver provides support for the built-in IDE controller on
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Toshiba Cell Reference Board.
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If unsure, say Y.
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endif
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config BLK_DEV_IDE_PMAC
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@ -800,14 +792,6 @@ config BLK_DEV_IDEDMA_PMAC
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to transfer data to and from memory. Saying Y is safe and improves
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performance.
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config BLK_DEV_IDE_CELLEB
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bool "Toshiba's Cell Reference Set IDE support"
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depends on PPC_CELLEB && IDE=y
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help
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This driver provides support for the built-in IDE controller on
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Toshiba Cell Reference Board.
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If unsure, say Y.
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config BLK_DEV_IDE_SWARM
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tristate "IDE for Sibyte evaluation boards"
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depends on SIBYTE_SB1xxx_SOC
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@ -851,19 +835,6 @@ config BLK_DEV_IDEDMA_ICS
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Say Y here if you want to add DMA (Direct Memory Access) support to
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the ICS IDE driver.
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config IDEDMA_ICS_AUTO
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bool "Use ICS DMA by default"
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depends on BLK_DEV_IDEDMA_ICS
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help
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Prior to kernel version 2.1.112, Linux used to automatically use
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DMA for IDE drives and chipsets which support it. Due to concerns
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about a couple of cases where buggy hardware may have caused damage,
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the default is now to NOT use DMA automatically. To revert to the
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previous behaviour, say Y to this question.
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If you suspect your hardware is at all flakey, say N here.
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Do NOT email the IDE kernel people regarding this issue!
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config BLK_DEV_IDE_RAPIDE
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tristate "RapIDE interface support"
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depends on ARM && ARCH_ACORN
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@ -1086,9 +1057,6 @@ config IDEDMA_IVB
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It is normally safe to answer Y; however, the default is N.
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config IDEDMA_AUTO
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def_bool IDEDMA_PCI_AUTO || IDEDMA_ICS_AUTO
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endif
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config BLK_DEV_HD_ONLY
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@ -37,7 +37,6 @@ ide-core-$(CONFIG_BLK_DEV_Q40IDE) += legacy/q40ide.o
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# built-in only drivers from ppc/
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ide-core-$(CONFIG_BLK_DEV_MPC8xx_IDE) += ppc/mpc8xx.o
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ide-core-$(CONFIG_BLK_DEV_IDE_PMAC) += ppc/pmac.o
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ide-core-$(CONFIG_BLK_DEV_IDE_CELLEB) += ppc/scc_pata.o
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# built-in only drivers from h8300/
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ide-core-$(CONFIG_H8300) += h8300/ide-h8300.o
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@ -196,11 +196,6 @@ static void icside_maskproc(ide_drive_t *drive, int mask)
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}
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#ifdef CONFIG_BLK_DEV_IDEDMA_ICS
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#ifndef CONFIG_IDEDMA_ICS_AUTO
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#warning CONFIG_IDEDMA_ICS_AUTO=n support is obsolete, and will be removed soon.
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#endif
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/*
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* SG-DMA support.
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*
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@ -474,12 +469,6 @@ static int icside_dma_lostirq(ide_drive_t *drive)
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static void icside_dma_init(ide_hwif_t *hwif)
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{
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int autodma = 0;
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#ifdef CONFIG_IDEDMA_ICS_AUTO
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autodma = 1;
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#endif
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printk(" %s: SG-DMA", hwif->name);
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hwif->atapi_dma = 1;
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@ -489,7 +478,7 @@ static void icside_dma_init(ide_hwif_t *hwif)
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hwif->dmatable_cpu = NULL;
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hwif->dmatable_dma = 0;
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hwif->speedproc = icside_set_speed;
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hwif->autodma = autodma;
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hwif->autodma = 1;
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hwif->ide_dma_check = icside_dma_check;
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hwif->dma_host_off = icside_dma_host_off;
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@ -767,7 +767,7 @@ int ide_set_dma(ide_drive_t *drive)
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switch(rc) {
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case -1: /* DMA needs to be disabled */
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hwif->dma_off_quietly(drive);
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return 0;
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return -1;
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case 0: /* DMA needs to be enabled */
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return hwif->ide_dma_on(drive);
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case 1: /* DMA setting cannot be changed */
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@ -177,11 +177,7 @@ DECLARE_MUTEX(ide_cfg_sem);
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static int ide_scan_direction; /* THIS was formerly 2.2.x pci=reverse */
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#endif
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#ifdef CONFIG_IDEDMA_AUTO
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int noautodma = 0;
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#else
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int noautodma = 1;
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#endif
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EXPORT_SYMBOL(noautodma);
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@ -639,6 +639,7 @@ static int au_ide_probe(struct device *dev)
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_auide_hwif *ahwif = &auide_hwif;
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ide_hwif_t *hwif;
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struct resource *res;
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hw_regs_t *hw;
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int ret = 0;
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#if defined(CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA)
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@ -681,7 +682,7 @@ static int au_ide_probe(struct device *dev)
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/* FIXME: This might possibly break PCMCIA IDE devices */
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hwif = &ide_hwifs[pdev->id];
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hw_regs_t *hw = &hwif->hw;
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hw = &hwif->hw;
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hwif->irq = hw->irq = ahwif->irq;
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hwif->chipset = ide_au1xxx;
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@ -3,6 +3,7 @@ obj-$(CONFIG_BLK_DEV_AEC62XX) += aec62xx.o
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obj-$(CONFIG_BLK_DEV_ALI15X3) += alim15x3.o
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obj-$(CONFIG_BLK_DEV_AMD74XX) += amd74xx.o
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obj-$(CONFIG_BLK_DEV_ATIIXP) += atiixp.o
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obj-$(CONFIG_BLK_DEV_CELLEB) += scc_pata.o
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obj-$(CONFIG_BLK_DEV_CMD64X) += cmd64x.o
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obj-$(CONFIG_BLK_DEV_CS5520) += cs5520.o
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obj-$(CONFIG_BLK_DEV_CS5530) += cs5530.o
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@ -1,6 +1,6 @@
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/* $Id: cmd64x.c,v 1.21 2000/01/30 23:23:16
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*
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* linux/drivers/ide/pci/cmd64x.c Version 1.41 Feb 3, 2007
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* linux/drivers/ide/pci/cmd64x.c Version 1.42 Feb 8, 2007
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*
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* cmd64x.c: Enable interrupts at initialization time on Ultra/PCI machines.
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* Note, this driver is not used at all on other systems because
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@ -189,6 +189,11 @@ static int cmd64x_get_info (char *buffer, char **addr, off_t offset, int count)
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#endif /* defined(DISPLAY_CMD64X_TIMINGS) && defined(CONFIG_PROC_FS) */
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static u8 quantize_timing(int timing, int quant)
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{
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return (timing + quant - 1) / quant;
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}
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/*
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* This routine writes the prepared setup/active/recovery counts
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* for a drive into the cmd646 chipset registers to active them.
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@ -268,47 +273,37 @@ static void program_drive_counts (ide_drive_t *drive, int setup_count, int activ
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*/
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static u8 cmd64x_tune_pio (ide_drive_t *drive, u8 mode_wanted)
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{
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int setup_time, active_time, recovery_time;
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int clock_time, pio_mode, cycle_time;
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u8 recovery_count2, cycle_count;
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int setup_count, active_count, recovery_count;
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int bus_speed = system_bus_clock();
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ide_pio_data_t d;
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int setup_time, active_time, cycle_time;
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u8 cycle_count, setup_count, active_count, recovery_count;
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u8 pio_mode;
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int clock_time = 1000 / system_bus_clock();
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ide_pio_data_t pio;
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pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &d);
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cycle_time = d.cycle_time;
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pio_mode = ide_get_best_pio_mode(drive, mode_wanted, 5, &pio);
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cycle_time = pio.cycle_time;
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/*
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* I copied all this complicated stuff from cmd640.c and made a few
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* minor changes. For now I am just going to pray that it is correct.
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*/
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setup_time = ide_pio_timings[pio_mode].setup_time;
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active_time = ide_pio_timings[pio_mode].active_time;
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recovery_time = cycle_time - (setup_time + active_time);
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clock_time = 1000 / bus_speed;
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cycle_count = (cycle_time + clock_time - 1) / clock_time;
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setup_count = (setup_time + clock_time - 1) / clock_time;
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setup_count = quantize_timing( setup_time, clock_time);
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cycle_count = quantize_timing( cycle_time, clock_time);
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active_count = quantize_timing(active_time, clock_time);
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active_count = (active_time + clock_time - 1) / clock_time;
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recovery_count = (recovery_time + clock_time - 1) / clock_time;
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recovery_count2 = cycle_count - (setup_count + active_count);
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if (recovery_count2 > recovery_count)
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recovery_count = recovery_count2;
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recovery_count = cycle_count - active_count;
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/* program_drive_counts() takes care of zero recovery cycles */
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if (recovery_count > 16) {
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active_count += recovery_count - 16;
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recovery_count = 16;
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}
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if (active_count > 16)
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active_count = 16; /* maximum allowed by cmd646 */
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active_count = 16; /* maximum allowed by cmd64x */
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program_drive_counts (drive, setup_count, active_count, recovery_count);
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cmdprintk("%s: PIO mode wanted %d, selected %d (%dns)%s, "
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"clocks=%d/%d/%d\n",
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drive->name, mode_wanted, pio_mode, cycle_time,
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d.overridden ? " (overriding vendor mode)" : "",
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pio.overridden ? " (overriding vendor mode)" : "",
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setup_count, active_count, recovery_count);
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return pio_mode;
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@ -240,12 +240,31 @@ static int __devinit jmicron_init_one(struct pci_dev *dev, const struct pci_devi
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return 0;
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}
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/* If libata is configured, jmicron PCI quirk will configure it such
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* that the SATA ports are in AHCI function while the PATA ports are
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* in a separate IDE function. In such cases, match device class and
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* attach only to IDE. If libata isn't configured, keep the old
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* behavior for backward compatibility.
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*/
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#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
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#define JMB_CLASS PCI_CLASS_STORAGE_IDE << 8
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#define JMB_CLASS_MASK 0xffff00
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#else
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#define JMB_CLASS 0
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#define JMB_CLASS_MASK 0
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#endif
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static struct pci_device_id jmicron_pci_tbl[] = {
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{ PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
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{ PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
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{ PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
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{ PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
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{ PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
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{ PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361,
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PCI_ANY_ID, PCI_ANY_ID, JMB_CLASS, JMB_CLASS_MASK, 0},
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{ PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363,
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PCI_ANY_ID, PCI_ANY_ID, JMB_CLASS, JMB_CLASS_MASK, 1},
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{ PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365,
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PCI_ANY_ID, PCI_ANY_ID, JMB_CLASS, JMB_CLASS_MASK, 2},
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{ PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366,
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PCI_ANY_ID, PCI_ANY_ID, JMB_CLASS, JMB_CLASS_MASK, 3},
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{ PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368,
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PCI_ANY_ID, PCI_ANY_ID, JMB_CLASS, JMB_CLASS_MASK, 4},
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{ 0, },
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};
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@ -505,11 +505,6 @@ static void ide_hwif_setup_dma(struct pci_dev *dev, ide_pci_device_t *d, ide_hwi
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}
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}
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}
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#ifndef CONFIG_IDEDMA_PCI_AUTO
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#warning CONFIG_IDEDMA_PCI_AUTO=n support is obsolete, and will be removed soon.
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#endif
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#endif /* CONFIG_BLK_DEV_IDEDMA_PCI*/
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/**
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@ -141,40 +141,6 @@ static int auide_ddma_init( _auide_hwif *auide );
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static void auide_setup_ports(hw_regs_t *hw, _auide_hwif *ahwif);
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int __init auide_probe(void);
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#ifdef CONFIG_PM
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int au1200ide_pm_callback( au1xxx_power_dev_t *dev,
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au1xxx_request_t request, void *data);
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static int au1xxxide_pm_standby( au1xxx_power_dev_t *dev );
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static int au1xxxide_pm_sleep( au1xxx_power_dev_t *dev );
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static int au1xxxide_pm_resume( au1xxx_power_dev_t *dev );
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static int au1xxxide_pm_getstatus( au1xxx_power_dev_t *dev );
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static int au1xxxide_pm_access( au1xxx_power_dev_t *dev );
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static int au1xxxide_pm_idle( au1xxx_power_dev_t *dev );
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static int au1xxxide_pm_cleanup( au1xxx_power_dev_t *dev );
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#endif
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/*
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* Multi-Word DMA + DbDMA functions
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*/
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#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
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static int auide_build_sglist(ide_drive_t *drive, struct request *rq);
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static int auide_build_dmatable(ide_drive_t *drive);
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static int auide_dma_end(ide_drive_t *drive);
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ide_startstop_t auide_dma_intr (ide_drive_t *drive);
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static void auide_dma_exec_cmd(ide_drive_t *drive, u8 command);
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static int auide_dma_setup(ide_drive_t *drive);
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static int auide_dma_check(ide_drive_t *drive);
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static int auide_dma_test_irq(ide_drive_t *drive);
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static int auide_dma_host_off(ide_drive_t *drive);
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static int auide_dma_host_on(ide_drive_t *drive);
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static int auide_dma_lostirq(ide_drive_t *drive);
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static int auide_dma_on(ide_drive_t *drive);
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static void auide_ddma_tx_callback(int irq, void *param);
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static void auide_ddma_rx_callback(int irq, void *param);
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static int auide_dma_off_quietly(ide_drive_t *drive);
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#endif /* end CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA */
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/*******************************************************************************
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* PIO Mode timing calculation : *
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* *
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