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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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net: phy: at803x: add device tree binding
Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Michael Walle
David S. Miller
parent
2c63221cd9
commit
2f664823a4
@ -13,7 +13,12 @@
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/of_gpio.h>
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#include <linux/bitfield.h>
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#include <linux/gpio/consumer.h>
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#include <linux/regulator/of_regulator.h>
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#include <linux/regulator/driver.h>
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#include <linux/regulator/consumer.h>
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#include <dt-bindings/net/qca-ar803x.h>
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#define AT803X_SPECIFIC_STATUS 0x11
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#define AT803X_SS_SPEED_MASK (3 << 14)
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@ -62,6 +67,42 @@
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#define AT803X_DEBUG_REG_5 0x05
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#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
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#define AT803X_DEBUG_REG_1F 0x1F
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#define AT803X_DEBUG_PLL_ON BIT(2)
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#define AT803X_DEBUG_RGMII_1V8 BIT(3)
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/* AT803x supports either the XTAL input pad, an internal PLL or the
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* DSP as clock reference for the clock output pad. The XTAL reference
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* is only used for 25 MHz output, all other frequencies need the PLL.
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* The DSP as a clock reference is used in synchronous ethernet
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* applications.
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*
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* By default the PLL is only enabled if there is a link. Otherwise
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* the PHY will go into low power state and disabled the PLL. You can
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* set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
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* enabled.
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*/
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#define AT803X_MMD7_CLK25M 0x8016
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#define AT803X_CLK_OUT_MASK GENMASK(4, 2)
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#define AT803X_CLK_OUT_25MHZ_XTAL 0
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#define AT803X_CLK_OUT_25MHZ_DSP 1
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#define AT803X_CLK_OUT_50MHZ_PLL 2
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#define AT803X_CLK_OUT_50MHZ_DSP 3
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#define AT803X_CLK_OUT_62_5MHZ_PLL 4
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#define AT803X_CLK_OUT_62_5MHZ_DSP 5
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#define AT803X_CLK_OUT_125MHZ_PLL 6
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#define AT803X_CLK_OUT_125MHZ_DSP 7
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/* The AR8035 has another mask which is compatible with the AR8031 mask but
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* doesn't support choosing between XTAL/PLL and DSP.
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*/
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#define AT8035_CLK_OUT_MASK GENMASK(4, 3)
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#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)
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#define AT803X_CLK_OUT_STRENGTH_FULL 0
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#define AT803X_CLK_OUT_STRENGTH_HALF 1
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#define AT803X_CLK_OUT_STRENGTH_QUARTER 2
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#define ATH9331_PHY_ID 0x004dd041
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#define ATH8030_PHY_ID 0x004dd076
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#define ATH8031_PHY_ID 0x004dd074
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@ -72,6 +113,16 @@ MODULE_DESCRIPTION("Atheros 803x PHY driver");
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MODULE_AUTHOR("Matus Ujhelyi");
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MODULE_LICENSE("GPL");
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struct at803x_priv {
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int flags;
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#define AT803X_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */
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u16 clk_25m_reg;
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u16 clk_25m_mask;
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struct regulator_dev *vddio_rdev;
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struct regulator_dev *vddh_rdev;
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struct regulator *vddio;
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};
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struct at803x_context {
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u16 bmcr;
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u16 advertise;
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@ -237,6 +288,238 @@ static int at803x_resume(struct phy_device *phydev)
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return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
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}
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static int at803x_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
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unsigned int selector)
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{
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struct phy_device *phydev = rdev_get_drvdata(rdev);
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if (selector)
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return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
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0, AT803X_DEBUG_RGMII_1V8);
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else
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return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
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AT803X_DEBUG_RGMII_1V8, 0);
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}
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static int at803x_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
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{
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struct phy_device *phydev = rdev_get_drvdata(rdev);
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int val;
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val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
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if (val < 0)
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return val;
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return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
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}
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static struct regulator_ops vddio_regulator_ops = {
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.list_voltage = regulator_list_voltage_table,
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.set_voltage_sel = at803x_rgmii_reg_set_voltage_sel,
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.get_voltage_sel = at803x_rgmii_reg_get_voltage_sel,
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};
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static const unsigned int vddio_voltage_table[] = {
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1500000,
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1800000,
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};
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static const struct regulator_desc vddio_desc = {
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.name = "vddio",
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.of_match = of_match_ptr("vddio-regulator"),
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.n_voltages = ARRAY_SIZE(vddio_voltage_table),
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.volt_table = vddio_voltage_table,
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.ops = &vddio_regulator_ops,
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.type = REGULATOR_VOLTAGE,
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.owner = THIS_MODULE,
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};
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static struct regulator_ops vddh_regulator_ops = {
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};
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static const struct regulator_desc vddh_desc = {
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.name = "vddh",
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.of_match = of_match_ptr("vddh-regulator"),
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.n_voltages = 1,
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.fixed_uV = 2500000,
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.ops = &vddh_regulator_ops,
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.type = REGULATOR_VOLTAGE,
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.owner = THIS_MODULE,
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};
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static int at8031_register_regulators(struct phy_device *phydev)
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{
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struct at803x_priv *priv = phydev->priv;
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struct device *dev = &phydev->mdio.dev;
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struct regulator_config config = { };
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config.dev = dev;
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config.driver_data = phydev;
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priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
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if (IS_ERR(priv->vddio_rdev)) {
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phydev_err(phydev, "failed to register VDDIO regulator\n");
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return PTR_ERR(priv->vddio_rdev);
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}
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priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
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if (IS_ERR(priv->vddh_rdev)) {
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phydev_err(phydev, "failed to register VDDH regulator\n");
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return PTR_ERR(priv->vddh_rdev);
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}
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return 0;
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}
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static bool at803x_match_phy_id(struct phy_device *phydev, u32 phy_id)
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{
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return (phydev->phy_id & phydev->drv->phy_id_mask)
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== (phy_id & phydev->drv->phy_id_mask);
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}
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static int at803x_parse_dt(struct phy_device *phydev)
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{
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struct device_node *node = phydev->mdio.dev.of_node;
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struct at803x_priv *priv = phydev->priv;
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unsigned int sel, mask;
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u32 freq, strength;
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int ret;
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if (!IS_ENABLED(CONFIG_OF_MDIO))
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return 0;
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ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
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if (!ret) {
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mask = AT803X_CLK_OUT_MASK;
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switch (freq) {
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case 25000000:
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sel = AT803X_CLK_OUT_25MHZ_XTAL;
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break;
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case 50000000:
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sel = AT803X_CLK_OUT_50MHZ_PLL;
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break;
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case 62500000:
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sel = AT803X_CLK_OUT_62_5MHZ_PLL;
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break;
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case 125000000:
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sel = AT803X_CLK_OUT_125MHZ_PLL;
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break;
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default:
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phydev_err(phydev, "invalid qca,clk-out-frequency\n");
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return -EINVAL;
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}
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priv->clk_25m_reg |= FIELD_PREP(mask, sel);
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priv->clk_25m_mask |= mask;
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/* Fixup for the AR8030/AR8035. This chip has another mask and
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* doesn't support the DSP reference. Eg. the lowest bit of the
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* mask. The upper two bits select the same frequencies. Mask
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* the lowest bit here.
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*
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* Warning:
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* There was no datasheet for the AR8030 available so this is
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* just a guess. But the AR8035 is listed as pin compatible
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* to the AR8030 so there might be a good chance it works on
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* the AR8030 too.
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*/
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if (at803x_match_phy_id(phydev, ATH8030_PHY_ID) ||
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at803x_match_phy_id(phydev, ATH8035_PHY_ID)) {
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priv->clk_25m_reg &= ~AT8035_CLK_OUT_MASK;
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priv->clk_25m_mask &= ~AT8035_CLK_OUT_MASK;
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}
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}
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ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
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if (!ret) {
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priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
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switch (strength) {
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case AR803X_STRENGTH_FULL:
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priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
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break;
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case AR803X_STRENGTH_HALF:
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priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
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break;
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case AR803X_STRENGTH_QUARTER:
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priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
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break;
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default:
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phydev_err(phydev, "invalid qca,clk-out-strength\n");
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return -EINVAL;
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}
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}
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/* Only supported on AR8031, the AR8030/AR8035 use strapping options */
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if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) {
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if (of_property_read_bool(node, "qca,keep-pll-enabled"))
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priv->flags |= AT803X_KEEP_PLL_ENABLED;
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ret = at8031_register_regulators(phydev);
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if (ret < 0)
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return ret;
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priv->vddio = devm_regulator_get_optional(&phydev->mdio.dev,
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"vddio");
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if (IS_ERR(priv->vddio)) {
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phydev_err(phydev, "failed to get VDDIO regulator\n");
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return PTR_ERR(priv->vddio);
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}
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ret = regulator_enable(priv->vddio);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int at803x_probe(struct phy_device *phydev)
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{
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struct device *dev = &phydev->mdio.dev;
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struct at803x_priv *priv;
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priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
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if (!priv)
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return -ENOMEM;
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phydev->priv = priv;
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return at803x_parse_dt(phydev);
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}
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static int at803x_clk_out_config(struct phy_device *phydev)
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{
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struct at803x_priv *priv = phydev->priv;
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int val;
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if (!priv->clk_25m_mask)
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return 0;
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val = phy_read_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M);
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if (val < 0)
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return val;
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val &= ~priv->clk_25m_mask;
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val |= priv->clk_25m_reg;
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return phy_write_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M, val);
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}
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static int at8031_pll_config(struct phy_device *phydev)
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{
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struct at803x_priv *priv = phydev->priv;
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/* The default after hardware reset is PLL OFF. After a soft reset, the
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* values are retained.
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*/
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if (priv->flags & AT803X_KEEP_PLL_ENABLED)
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return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
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0, AT803X_DEBUG_PLL_ON);
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else
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return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
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AT803X_DEBUG_PLL_ON, 0);
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}
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static int at803x_config_init(struct phy_device *phydev)
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{
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int ret;
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@ -259,8 +542,20 @@ static int at803x_config_init(struct phy_device *phydev)
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ret = at803x_enable_tx_delay(phydev);
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else
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ret = at803x_disable_tx_delay(phydev);
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if (ret < 0)
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return ret;
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return ret;
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ret = at803x_clk_out_config(phydev);
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if (ret < 0)
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return ret;
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if (at803x_match_phy_id(phydev, ATH8031_PHY_ID)) {
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ret = at8031_pll_config(phydev);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int at803x_ack_interrupt(struct phy_device *phydev)
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@ -413,6 +708,7 @@ static struct phy_driver at803x_driver[] = {
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.phy_id = ATH8035_PHY_ID,
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.name = "Atheros 8035 ethernet",
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.phy_id_mask = AT803X_PHY_ID_MASK,
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.probe = at803x_probe,
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.config_init = at803x_config_init,
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.set_wol = at803x_set_wol,
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.get_wol = at803x_get_wol,
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@ -427,6 +723,7 @@ static struct phy_driver at803x_driver[] = {
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.phy_id = ATH8030_PHY_ID,
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.name = "Atheros 8030 ethernet",
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.phy_id_mask = AT803X_PHY_ID_MASK,
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.probe = at803x_probe,
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.config_init = at803x_config_init,
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.link_change_notify = at803x_link_change_notify,
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.set_wol = at803x_set_wol,
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@ -441,6 +738,7 @@ static struct phy_driver at803x_driver[] = {
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.phy_id = ATH8031_PHY_ID,
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.name = "Atheros 8031 ethernet",
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.phy_id_mask = AT803X_PHY_ID_MASK,
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.probe = at803x_probe,
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.config_init = at803x_config_init,
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.set_wol = at803x_set_wol,
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.get_wol = at803x_get_wol,
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@ -455,6 +753,7 @@ static struct phy_driver at803x_driver[] = {
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/* ATHEROS AR9331 */
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PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
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.name = "Atheros AR9331 built-in PHY",
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.probe = at803x_probe,
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.config_init = at803x_config_init,
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.suspend = at803x_suspend,
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.resume = at803x_resume,
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