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ARM: dts: qcom: Move common nodes to ipq8064-v.1.0.dtsi

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The nodes in ipq8064-ap148.dts currently are common with
boards that we will add next. So move the common data to
ipq8064-v.1.0.dtsi.

Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This commit is contained in:
Sricharan R 2018-08-03 19:40:17 +05:30 committed by Andy Gross
parent f14c558892
commit 2e7a2c9101
3 changed files with 77 additions and 80 deletions
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83
arch/arm/boot/dts/qcom-ipq8064-ap148.dts
View File

@ -2,26 +2,8 @@
#include "qcom-ipq8064-v1.0.dtsi"
/ {
model = "Qualcomm IPQ8064/AP148";
compatible = "qcom,ipq8064-ap148", "qcom,ipq8064";
aliases {
serial0 = &gsbi4_serial;
};
chosen {
stdout-path = "serial0:115200n8";
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
rsvd@41200000 {
reg = <0x41200000 0x300000>;
no-map;
};
};
model = "Qualcomm Technologies, Inc. IPQ8064/AP-148";
compatible = "qcom,ipq8064-ap148";
soc {
pinmux@800000 {
@ -30,74 +12,15 @@ i2c4_pins: i2c4_pinmux {
function = "gsbi4";
bias-disable;
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
drive-strength = <10>;
bias-none;
};
};
};
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
i2c@16380000 {
status = "ok";
serial@16340000 {
status = "ok";
};
i2c4: i2c@16380000 {
status = "ok";
clock-frequency = <200000>;
pinctrl-0 = <&i2c4_pins>;
pinctrl-names = "default";
};
};
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
status = "ok";
spi4: spi@1a280000 {
status = "ok";
spi-max-frequency = <50000000>;
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 0>;
flash: m25p80@0 {
compatible = "s25fl256s1";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
partition@0 {
label = "rootfs";
reg = <0x0 0x1000000>;
};
partition@1 {
label = "scratch";
reg = <0x1000000 0x1000000>;
};
};
};
};
sata-phy@1b400000 {
status = "ok";
};
sata@29000000 {
ports-implemented = <0x1>;
status = "ok";
};
};
};

65
arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi
View File

@ -1,2 +1,67 @@
// SPDX-License-Identifier: GPL-2.0
#include "qcom-ipq8064.dtsi"
/ {
model = "Qualcomm Technologies, Inc. IPQ8064-v1.0";
aliases {
serial0 = &gsbi4_serial;
};
chosen {
stdout-path = "serial0:115200n8";
};
soc {
gsbi@16300000 {
qcom,mode = <GSBI_PROT_I2C_UART>;
status = "ok";
serial@16340000 {
status = "ok";
};
};
gsbi5: gsbi@1a200000 {
qcom,mode = <GSBI_PROT_SPI>;
status = "ok";
spi4: spi@1a280000 {
status = "ok";
spi-max-frequency = <50000000>;
pinctrl-0 = <&spi_pins>;
pinctrl-names = "default";
cs-gpios = <&qcom_pinmux 20 0>;
flash: m25p80@0 {
compatible = "s25fl256s1";
#address-cells = <1>;
#size-cells = <1>;
spi-max-frequency = <50000000>;
reg = <0>;
partition@0 {
label = "rootfs";
reg = <0x0 0x1000000>;
};
partition@1 {
label = "scratch";
reg = <0x1000000 0x1000000>;
};
};
};
};
sata-phy@1b400000 {
status = "ok";
};
sata@29000000 {
ports-implemented = <0x1>;
status = "ok";
};
};
};

9
arch/arm/boot/dts/qcom-ipq8064.dtsi
View File

@ -144,6 +144,15 @@ mux {
bias-disable;
};
};
spi_pins: spi_pins {
mux {
pins = "gpio18", "gpio19", "gpio21";
function = "gsbi5";
drive-strength = <10>;
bias-none;
};
};
};
intc: interrupt-controller@2000000 {