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drm/mgag200: Move TAGFIFO reset into separate function

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The TAGFIFO state is now reset in mgag200_g200er_reset_tagfifo().

v2:
	* define MGAREG_SEQ1_SCROFF

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Tested-by: John Donnelly <John.p.donnelly@oracle.com>
Acked-by: Sam Ravnborg <sam@ravnborg.org>
Acked-by: Emil Velikov <emil.velikov@collabora.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200515083233.32036-10-tzimmermann@suse.de
This commit is contained in:
Thomas Zimmermann 2020-05-15 10:32:27 +02:00
parent 836d536881
commit 2e5ccbbaea
3 changed files with 38 additions and 16 deletions
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6
drivers/gpu/drm/mgag200/mgag200_drv.h
View File

@ -49,6 +49,12 @@
WREG8(ATTR_DATA, v); \
} while (0) \
#define RREG_SEQ(reg, v) \
do { \
WREG8(MGAREG_SEQ_INDEX, reg); \
v = RREG8(MGAREG_SEQ_DATA); \
} while (0) \
#define WREG_SEQ(reg, v) \
do { \
WREG8(MGAREG_SEQ_INDEX, reg); \

45
drivers/gpu/drm/mgag200/mgag200_mode.c
View File

@ -1106,6 +1106,33 @@ static void mgag200_set_format_regs(struct mga_device *mdev,
WREG_ECRT(3, crtcext3);
}
static void mgag200_g200er_reset_tagfifo(struct mga_device *mdev)
{
static uint32_t RESET_FLAG = 0x00200000; /* undocumented magic value */
u8 seq1;
u32 memctl;
/* screen off */
RREG_SEQ(0x01, seq1);
seq1 |= MGAREG_SEQ1_SCROFF;
WREG_SEQ(0x01, seq1);
memctl = RREG32(MGAREG_MEMCTL);
memctl |= RESET_FLAG;
WREG32(MGAREG_MEMCTL, memctl);
udelay(1000);
memctl &= ~RESET_FLAG;
WREG32(MGAREG_MEMCTL, memctl);
/* screen on */
RREG_SEQ(0x01, seq1);
seq1 &= ~MGAREG_SEQ1_SCROFF;
WREG_SEQ(0x01, seq1);
}
static int mga_crtc_mode_set(struct drm_crtc *crtc,
struct drm_display_mode *mode,
struct drm_display_mode *adjusted_mode,
@ -1240,22 +1267,8 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
mgag200_set_mode_regs(mdev, mode);
/* reset tagfifo */
if (mdev->type == G200_ER) {
u32 mem_ctl = RREG32(MGAREG_MEMCTL);
u8 seq1;
/* screen off */
WREG8(MGAREG_SEQ_INDEX, 0x01);
seq1 = RREG8(MGAREG_SEQ_DATA) | 0x20;
WREG8(MGAREG_SEQ_DATA, seq1);
WREG32(MGAREG_MEMCTL, mem_ctl | 0x00200000);
udelay(1000);
WREG32(MGAREG_MEMCTL, mem_ctl & ~0x00200000);
WREG8(MGAREG_SEQ_DATA, seq1 & ~0x20);
}
if (mdev->type == G200_ER)
mgag200_g200er_reset_tagfifo(mdev);
if (IS_G200_SE(mdev)) {

3
drivers/gpu/drm/mgag200/mgag200_reg.h
View File

@ -235,6 +235,9 @@
/* MMIO VGA registers */
#define MGAREG_SEQ_INDEX 0x1fc4
#define MGAREG_SEQ_DATA 0x1fc5
#define MGAREG_SEQ1_SCROFF BIT(5)
#define MGAREG_CRTC_INDEX 0x1fd4
#define MGAREG_CRTC_DATA 0x1fd5
#define MGAREG_CRTCEXT_INDEX 0x1fde