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net: atlantic: QoS implementation: min_rate
This patch adds support for mqprio min_rate limiters. A2 HW supports Weighted Strict Priority (WSP) arbitration for Tx Descriptor Queue scheduling among TCs, which can be used for min_rate shaping. Signed-off-by: Mark Starovoytov <mstarovoitov@marvell.com> Signed-off-by: Igor Russkikh <irusskikh@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Mark Starovoytov
David S. Miller
parent
b64f2ac995
commit
2deac71ac4
@ -280,6 +280,8 @@ struct aq_hw_ops {
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int (*hw_rss_hash_set)(struct aq_hw_s *self,
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struct aq_rss_parameters *rss_params);
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int (*hw_tc_rate_limit_set)(struct aq_hw_s *self);
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int (*hw_get_regs)(struct aq_hw_s *self,
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const struct aq_hw_caps_s *aq_hw_caps,
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u32 *regs_buff);
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@ -340,7 +340,6 @@ static int aq_validate_mqprio_opt(struct aq_nic_s *self,
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struct aq_nic_cfg_s *aq_nic_cfg = aq_nic_get_cfg(self);
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const unsigned int tcs_max = min_t(u8, aq_nic_cfg->aq_hw_caps->tcs_max,
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AQ_CFG_TCS_MAX);
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int i;
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if (num_tc > tcs_max) {
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netdev_err(self->ndev, "Too many TCs requested\n");
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@ -352,12 +351,9 @@ static int aq_validate_mqprio_opt(struct aq_nic_s *self,
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return -EOPNOTSUPP;
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}
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for (i = 0; i < num_tc; i++) {
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if (has_min_rate && mqprio->min_rate[i]) {
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netdev_err(self->ndev,
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"Min tx rate is not supported\n");
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return -EOPNOTSUPP;
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}
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if (has_min_rate && !ATL_HW_IS_CHIP_FEATURE(self->aq_hw, ANTIGUA)) {
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netdev_err(self->ndev, "Min tx rate is not supported\n");
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return -EOPNOTSUPP;
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}
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return 0;
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@ -368,23 +364,35 @@ static int aq_ndo_setup_tc(struct net_device *dev, enum tc_setup_type type,
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{
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struct tc_mqprio_qopt_offload *mqprio = type_data;
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struct aq_nic_s *aq_nic = netdev_priv(dev);
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bool has_min_rate;
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bool has_max_rate;
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int err;
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int i;
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if (type != TC_SETUP_QDISC_MQPRIO)
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return -EOPNOTSUPP;
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has_min_rate = !!(mqprio->flags & TC_MQPRIO_F_MIN_RATE);
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has_max_rate = !!(mqprio->flags & TC_MQPRIO_F_MAX_RATE);
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err = aq_validate_mqprio_opt(aq_nic, mqprio, mqprio->qopt.num_tc);
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if (err)
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return err;
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if (mqprio->flags & TC_MQPRIO_F_MAX_RATE) {
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for (i = 0; i < mqprio->qopt.num_tc; i++) {
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for (i = 0; i < mqprio->qopt.num_tc; i++) {
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if (has_max_rate) {
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u64 max_rate = mqprio->max_rate[i];
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do_div(max_rate, AQ_MBPS_DIVISOR);
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aq_nic_setup_tc_max_rate(aq_nic, i, (u32)max_rate);
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}
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if (has_min_rate) {
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u64 min_rate = mqprio->min_rate[i];
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do_div(min_rate, AQ_MBPS_DIVISOR);
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aq_nic_setup_tc_min_rate(aq_nic, i, (u32)min_rate);
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}
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}
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return aq_nic_setup_tc_mqprio(aq_nic, mqprio->qopt.num_tc,
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@ -196,6 +196,9 @@ static int aq_nic_update_link_status(struct aq_nic_s *self)
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#if IS_ENABLED(CONFIG_MACSEC)
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aq_macsec_enable(self);
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#endif
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if (self->aq_hw_ops->hw_tc_rate_limit_set)
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self->aq_hw_ops->hw_tc_rate_limit_set(self->aq_hw);
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netif_tx_wake_all_queues(self->ndev);
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}
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if (netif_carrier_ok(self->ndev) && !self->link_status.mbps) {
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@ -1374,3 +1377,28 @@ int aq_nic_setup_tc_max_rate(struct aq_nic_s *self, const unsigned int tc,
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return 0;
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}
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int aq_nic_setup_tc_min_rate(struct aq_nic_s *self, const unsigned int tc,
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const u32 min_rate)
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{
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struct aq_nic_cfg_s *cfg = &self->aq_nic_cfg;
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if (tc >= AQ_CFG_TCS_MAX)
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return -EINVAL;
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if (min_rate)
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set_bit(tc, &cfg->tc_min_rate_msk);
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else
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clear_bit(tc, &cfg->tc_min_rate_msk);
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if (min_rate && min_rate < 20) {
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netdev_warn(self->ndev,
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"Setting %s to the minimum usable value of %dMbps.\n",
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"min rate", 20);
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cfg->tc_min_rate[tc] = 20;
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} else {
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cfg->tc_min_rate[tc] = min_rate;
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}
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return 0;
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}
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@ -66,6 +66,8 @@ struct aq_nic_cfg_s {
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u8 tcs;
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u8 prio_tc_map[8];
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u32 tc_max_rate[AQ_CFG_TCS_MAX];
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unsigned long tc_min_rate_msk;
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u32 tc_min_rate[AQ_CFG_TCS_MAX];
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struct aq_rss_parameters aq_rss;
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u32 eee_speeds;
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};
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@ -198,4 +200,6 @@ void aq_nic_release_filter(struct aq_nic_s *self, enum aq_rx_filter_type type,
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int aq_nic_setup_tc_mqprio(struct aq_nic_s *self, u32 tcs, u8 *prio_tc_map);
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int aq_nic_setup_tc_max_rate(struct aq_nic_s *self, const unsigned int tc,
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const u32 max_rate);
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int aq_nic_setup_tc_min_rate(struct aq_nic_s *self, const unsigned int tc,
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const u32 min_rate);
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#endif /* AQ_NIC_H */
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@ -138,8 +138,6 @@ static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
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unsigned int prio = 0U;
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u32 tc = 0U;
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hw_atl_b0_hw_init_tx_tc_rate_limit(self);
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if (cfg->is_ptp) {
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tx_buff_size -= HW_ATL_B0_PTP_TXBUF_SIZE;
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rx_buff_size -= HW_ATL_B0_PTP_RXBUF_SIZE;
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@ -152,18 +150,11 @@ static int hw_atl_b0_hw_qos_set(struct aq_hw_s *self)
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/* TPS VM init */
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hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
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/* TPS TC credits init */
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hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
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tx_buff_size /= cfg->tcs;
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rx_buff_size /= cfg->tcs;
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for (tc = 0; tc < cfg->tcs; tc++) {
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u32 threshold = 0U;
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/* TX Packet Scheduler Data TC0 */
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hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, tc, 0xFFF);
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hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, tc, 0x64);
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/* Tx buf size TC0 */
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hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, tx_buff_size, tc);
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@ -319,24 +310,87 @@ int hw_atl_b0_hw_offload_set(struct aq_hw_s *self,
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return aq_hw_err_from_flags(self);
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}
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int hw_atl_b0_hw_init_tx_tc_rate_limit(struct aq_hw_s *self)
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static int hw_atl_b0_hw_init_tx_tc_rate_limit(struct aq_hw_s *self)
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{
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static const u32 max_weight = BIT(HW_ATL_TPS_DATA_TCTWEIGHT_WIDTH) - 1;
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/* Scale factor is based on the number of bits in fractional portion */
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static const u32 scale = BIT(HW_ATL_TPS_DESC_RATE_Y_WIDTH);
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static const u32 frac_msk = HW_ATL_TPS_DESC_RATE_Y_MSK >>
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HW_ATL_TPS_DESC_RATE_Y_SHIFT;
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const u32 link_speed = self->aq_link_status.mbps;
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struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg;
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unsigned long num_min_rated_tcs = 0;
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u32 tc_weight[AQ_CFG_TCS_MAX];
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u32 fixed_max_credit;
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u8 min_rate_msk = 0;
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u32 sum_weight = 0;
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int tc;
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/* By default max_credit is based upon MTU (in unit of 64b) */
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fixed_max_credit = nic_cfg->aq_hw_caps->mtu / 64;
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if (link_speed) {
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min_rate_msk = nic_cfg->tc_min_rate_msk &
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(BIT(nic_cfg->tcs) - 1);
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num_min_rated_tcs = hweight8(min_rate_msk);
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}
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/* First, calculate weights where min_rate is specified */
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if (num_min_rated_tcs) {
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for (tc = 0; tc != nic_cfg->tcs; tc++) {
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if (!nic_cfg->tc_min_rate[tc]) {
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tc_weight[tc] = 0;
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continue;
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}
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tc_weight[tc] = (-1L + link_speed +
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nic_cfg->tc_min_rate[tc] *
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max_weight) /
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link_speed;
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tc_weight[tc] = min(tc_weight[tc], max_weight);
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sum_weight += tc_weight[tc];
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}
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}
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/* WSP, if min_rate is set for at least one TC.
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* RR otherwise.
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*/
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hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, min_rate_msk ? 1U : 0U);
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/* Data TC Arbiter takes precedence over Descriptor TC Arbiter,
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* leave Descriptor TC Arbiter as RR.
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*/
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hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
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hw_atl_tps_tx_desc_rate_mode_set(self, nic_cfg->is_qos ? 1U : 0U);
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for (tc = 0; tc != nic_cfg->tcs; tc++) {
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const u32 en = (nic_cfg->tc_max_rate[tc] != 0) ? 1U : 0U;
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const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0);
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u32 weight, max_credit;
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hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, tc, 0x50);
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hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, tc,
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fixed_max_credit);
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hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, tc, 0x1E);
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if (num_min_rated_tcs) {
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weight = tc_weight[tc];
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if (!weight && sum_weight < max_weight)
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weight = (max_weight - sum_weight) /
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(nic_cfg->tcs - num_min_rated_tcs);
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else if (!weight)
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weight = 0x64;
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max_credit = max(8 * weight, fixed_max_credit);
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} else {
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weight = 0x64;
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max_credit = 0xFFF;
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}
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hw_atl_tps_tx_pkt_shed_tc_data_weight_set(self, tc, weight);
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hw_atl_tps_tx_pkt_shed_tc_data_max_credit_set(self, tc,
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max_credit);
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hw_atl_tps_tx_desc_rate_en_set(self, desc, en);
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if (en) {
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@ -1550,6 +1604,7 @@ const struct aq_hw_ops hw_atl_ops_b0 = {
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.hw_interrupt_moderation_set = hw_atl_b0_hw_interrupt_moderation_set,
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.hw_rss_set = hw_atl_b0_hw_rss_set,
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.hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set,
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.hw_tc_rate_limit_set = hw_atl_b0_hw_init_tx_tc_rate_limit,
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.hw_get_regs = hw_atl_utils_hw_get_regs,
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.hw_get_hw_stats = hw_atl_utils_get_hw_stats,
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.hw_get_fw_version = hw_atl_utils_get_fw_version,
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@ -62,8 +62,6 @@ int hw_atl_b0_hw_mac_addr_set(struct aq_hw_s *self, u8 *mac_addr);
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int hw_atl_b0_hw_start(struct aq_hw_s *self);
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int hw_atl_b0_hw_init_tx_tc_rate_limit(struct aq_hw_s *self);
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int hw_atl_b0_hw_irq_enable(struct aq_hw_s *self, u64 mask);
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int hw_atl_b0_hw_irq_disable(struct aq_hw_s *self, u64 mask);
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int hw_atl_b0_hw_irq_read(struct aq_hw_s *self, u64 *mask);
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@ -10,6 +10,7 @@
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#include "hw_atl/hw_atl_b0.h"
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#include "hw_atl/hw_atl_utils.h"
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#include "hw_atl/hw_atl_llh.h"
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#include "hw_atl/hw_atl_llh_internal.h"
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#include "hw_atl2_utils.h"
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#include "hw_atl2_llh.h"
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#include "hw_atl2_internal.h"
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@ -148,8 +149,6 @@ static int hw_atl2_hw_qos_set(struct aq_hw_s *self)
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unsigned int prio = 0U;
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u32 tc = 0U;
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hw_atl_b0_hw_init_tx_tc_rate_limit(self);
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/* TPS Descriptor rate init */
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hw_atl_tps_tx_pkt_shed_desc_rate_curr_time_res_set(self, 0x0U);
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hw_atl_tps_tx_pkt_shed_desc_rate_lim_set(self, 0xA);
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@ -157,19 +156,11 @@ static int hw_atl2_hw_qos_set(struct aq_hw_s *self)
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/* TPS VM init */
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hw_atl_tps_tx_pkt_shed_desc_vm_arb_mode_set(self, 0U);
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/* TPS TC credits init */
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hw_atl_tps_tx_pkt_shed_data_arb_mode_set(self, 0U);
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tx_buff_size /= cfg->tcs;
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rx_buff_size /= cfg->tcs;
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for (tc = 0; tc < cfg->tcs; tc++) {
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u32 threshold = 0U;
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/* TX Packet Scheduler Data TC0 */
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hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(self, 0xFFF0,
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tc);
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hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(self, 0x640, tc);
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/* Tx buf size TC0 */
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hw_atl_tpb_tx_pkt_buff_size_per_tc_set(self, tx_buff_size, tc);
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@ -225,6 +216,121 @@ static int hw_atl2_hw_rss_set(struct aq_hw_s *self,
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return aq_hw_err_from_flags(self);
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}
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static int hw_atl2_hw_init_tx_tc_rate_limit(struct aq_hw_s *self)
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{
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static const u32 max_weight = BIT(HW_ATL2_TPS_DATA_TCTWEIGHT_WIDTH) - 1;
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/* Scale factor is based on the number of bits in fractional portion */
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static const u32 scale = BIT(HW_ATL_TPS_DESC_RATE_Y_WIDTH);
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static const u32 frac_msk = HW_ATL_TPS_DESC_RATE_Y_MSK >>
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HW_ATL_TPS_DESC_RATE_Y_SHIFT;
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const u32 link_speed = self->aq_link_status.mbps;
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struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg;
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unsigned long num_min_rated_tcs = 0;
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u32 tc_weight[AQ_CFG_TCS_MAX];
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u32 fixed_max_credit_4b;
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u32 fixed_max_credit;
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u8 min_rate_msk = 0;
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u32 sum_weight = 0;
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int tc;
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/* By default max_credit is based upon MTU (in unit of 64b) */
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fixed_max_credit = nic_cfg->aq_hw_caps->mtu / 64;
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/* in unit of 4b */
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fixed_max_credit_4b = nic_cfg->aq_hw_caps->mtu / 4;
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if (link_speed) {
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min_rate_msk = nic_cfg->tc_min_rate_msk &
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(BIT(nic_cfg->tcs) - 1);
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num_min_rated_tcs = hweight8(min_rate_msk);
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}
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/* First, calculate weights where min_rate is specified */
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if (num_min_rated_tcs) {
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for (tc = 0; tc != nic_cfg->tcs; tc++) {
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if (!nic_cfg->tc_min_rate[tc]) {
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tc_weight[tc] = 0;
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continue;
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}
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tc_weight[tc] = (-1L + link_speed +
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nic_cfg->tc_min_rate[tc] *
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max_weight) /
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link_speed;
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tc_weight[tc] = min(tc_weight[tc], max_weight);
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sum_weight += tc_weight[tc];
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}
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}
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/* WSP, if min_rate is set for at least one TC.
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* RR otherwise.
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*/
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hw_atl2_tps_tx_pkt_shed_data_arb_mode_set(self, min_rate_msk ? 1U : 0U);
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/* Data TC Arbiter takes precedence over Descriptor TC Arbiter,
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* leave Descriptor TC Arbiter as RR.
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*/
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hw_atl_tps_tx_pkt_shed_desc_tc_arb_mode_set(self, 0U);
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hw_atl_tps_tx_desc_rate_mode_set(self, nic_cfg->is_qos ? 1U : 0U);
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for (tc = 0; tc != nic_cfg->tcs; tc++) {
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const u32 en = (nic_cfg->tc_max_rate[tc] != 0) ? 1U : 0U;
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const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0);
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u32 weight, max_credit;
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hw_atl_tps_tx_pkt_shed_desc_tc_max_credit_set(self, tc,
|
||||
fixed_max_credit);
|
||||
hw_atl_tps_tx_pkt_shed_desc_tc_weight_set(self, tc, 0x1E);
|
||||
|
||||
if (num_min_rated_tcs) {
|
||||
weight = tc_weight[tc];
|
||||
|
||||
if (!weight && sum_weight < max_weight)
|
||||
weight = (max_weight - sum_weight) /
|
||||
(nic_cfg->tcs - num_min_rated_tcs);
|
||||
else if (!weight)
|
||||
weight = 0x640;
|
||||
|
||||
max_credit = max(2 * weight, fixed_max_credit_4b);
|
||||
} else {
|
||||
weight = 0x640;
|
||||
max_credit = 0xFFF0;
|
||||
}
|
||||
|
||||
hw_atl2_tps_tx_pkt_shed_tc_data_weight_set(self, tc, weight);
|
||||
hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(self, tc,
|
||||
max_credit);
|
||||
|
||||
hw_atl_tps_tx_desc_rate_en_set(self, desc, en);
|
||||
|
||||
if (en) {
|
||||
/* Nominal rate is always 10G */
|
||||
const u32 rate = 10000U * scale /
|
||||
nic_cfg->tc_max_rate[tc];
|
||||
const u32 rate_int = rate >>
|
||||
HW_ATL_TPS_DESC_RATE_Y_WIDTH;
|
||||
const u32 rate_frac = rate & frac_msk;
|
||||
|
||||
hw_atl_tps_tx_desc_rate_x_set(self, desc, rate_int);
|
||||
hw_atl_tps_tx_desc_rate_y_set(self, desc, rate_frac);
|
||||
} else {
|
||||
/* A value of 1 indicates the queue is not
|
||||
* rate controlled.
|
||||
*/
|
||||
hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U);
|
||||
hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U);
|
||||
}
|
||||
}
|
||||
for (tc = nic_cfg->tcs; tc != AQ_CFG_TCS_MAX; tc++) {
|
||||
const u32 desc = AQ_NIC_CFG_TCVEC2RING(nic_cfg, tc, 0);
|
||||
|
||||
hw_atl_tps_tx_desc_rate_en_set(self, desc, 0U);
|
||||
hw_atl_tps_tx_desc_rate_x_set(self, desc, 1U);
|
||||
hw_atl_tps_tx_desc_rate_y_set(self, desc, 0U);
|
||||
}
|
||||
|
||||
return aq_hw_err_from_flags(self);
|
||||
}
|
||||
|
||||
static int hw_atl2_hw_init_tx_path(struct aq_hw_s *self)
|
||||
{
|
||||
struct aq_nic_cfg_s *nic_cfg = self->aq_nic_cfg;
|
||||
@ -730,6 +836,7 @@ const struct aq_hw_ops hw_atl2_ops = {
|
||||
.hw_interrupt_moderation_set = hw_atl2_hw_interrupt_moderation_set,
|
||||
.hw_rss_set = hw_atl2_hw_rss_set,
|
||||
.hw_rss_hash_set = hw_atl_b0_hw_rss_hash_set,
|
||||
.hw_tc_rate_limit_set = hw_atl2_hw_init_tx_tc_rate_limit,
|
||||
.hw_get_hw_stats = hw_atl2_utils_get_hw_stats,
|
||||
.hw_get_fw_version = hw_atl2_utils_get_fw_version,
|
||||
.hw_set_offload = hw_atl_b0_hw_offload_set,
|
||||
|
||||
@ -93,6 +93,15 @@ void hw_atl2_reg_tx_intr_moder_ctrl_set(struct aq_hw_s *aq_hw,
|
||||
tx_intr_moderation_ctl);
|
||||
}
|
||||
|
||||
void hw_atl2_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
|
||||
const u32 data_arb_mode)
|
||||
{
|
||||
aq_hw_write_reg_bit(aq_hw, HW_ATL2_TPS_DATA_TC_ARB_MODE_ADR,
|
||||
HW_ATL2_TPS_DATA_TC_ARB_MODE_MSK,
|
||||
HW_ATL2_TPS_DATA_TC_ARB_MODE_SHIFT,
|
||||
data_arb_mode);
|
||||
}
|
||||
|
||||
void hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
|
||||
const u32 tc,
|
||||
const u32 max_credit)
|
||||
|
||||
@ -45,6 +45,9 @@ void hw_atl2_tpb_tx_tc_q_rand_map_en_set(struct aq_hw_s *aq_hw,
|
||||
/* set tx buffer clock gate enable */
|
||||
void hw_atl2_tpb_tx_buf_clk_gate_en_set(struct aq_hw_s *aq_hw, u32 clk_gate_en);
|
||||
|
||||
void hw_atl2_tps_tx_pkt_shed_data_arb_mode_set(struct aq_hw_s *aq_hw,
|
||||
const u32 data_arb_mode);
|
||||
|
||||
/* set tx packet scheduler tc data max credit */
|
||||
void hw_atl2_tps_tx_pkt_shed_tc_data_max_credit_set(struct aq_hw_s *aq_hw,
|
||||
const u32 tc,
|
||||
|
||||
@ -185,42 +185,60 @@
|
||||
/* default value of bitfield tx_q_tc_map{q} */
|
||||
#define HW_ATL2_TX_Q_TC_MAP_DEFAULT 0x0
|
||||
|
||||
/* tx data_tc_arb_mode bitfield definitions
|
||||
* preprocessor definitions for the bitfield "data_tc_arb_mode".
|
||||
* port="pif_tps_data_tc_arb_mode_i"
|
||||
*/
|
||||
|
||||
/* register address for bitfield data_tc_arb_mode */
|
||||
#define HW_ATL2_TPS_DATA_TC_ARB_MODE_ADR 0x00007100
|
||||
/* bitmask for bitfield data_tc_arb_mode */
|
||||
#define HW_ATL2_TPS_DATA_TC_ARB_MODE_MSK 0x00000003
|
||||
/* inverted bitmask for bitfield data_tc_arb_mode */
|
||||
#define HW_ATL2_TPS_DATA_TC_ARB_MODE_MSKN 0xfffffffc
|
||||
/* lower bit position of bitfield data_tc_arb_mode */
|
||||
#define HW_ATL2_TPS_DATA_TC_ARB_MODE_SHIFT 0
|
||||
/* width of bitfield data_tc_arb_mode */
|
||||
#define HW_ATL2_TPS_DATA_TC_ARB_MODE_WIDTH 2
|
||||
/* default value of bitfield data_tc_arb_mode */
|
||||
#define HW_ATL2_TPS_DATA_TC_ARB_MODE_DEFAULT 0x0
|
||||
|
||||
/* tx data_tc{t}_credit_max[f:0] bitfield definitions
|
||||
* preprocessor definitions for the bitfield "data_tc{t}_credit_max[f:0]".
|
||||
* parameter: tc {t} | stride size 0x4 | range [0, 7]
|
||||
* port="pif_tps_data_tc0_credit_max_i[11:0]"
|
||||
* port="pif_tps_data_tc0_credit_max_i[15:0]"
|
||||
*/
|
||||
|
||||
/* register address for bitfield data_tc{t}_credit_max[b:0] */
|
||||
/* register address for bitfield data_tc{t}_credit_max[f:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_ADR(tc) (0x00007110 + (tc) * 0x4)
|
||||
/* bitmask for bitfield data_tc{t}_credit_max[b:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSK 0x0fff0000
|
||||
/* inverted bitmask for bitfield data_tc{t}_credit_max[b:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSKN 0xf000ffff
|
||||
/* lower bit position of bitfield data_tc{t}_credit_max[b:0] */
|
||||
/* bitmask for bitfield data_tc{t}_credit_max[f:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSK 0xffff0000
|
||||
/* inverted bitmask for bitfield data_tc{t}_credit_max[f:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_MSKN 0x0000ffff
|
||||
/* lower bit position of bitfield data_tc{t}_credit_max[f:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_SHIFT 16
|
||||
/* width of bitfield data_tc{t}_credit_max[b:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_WIDTH 12
|
||||
/* default value of bitfield data_tc{t}_credit_max[b:0] */
|
||||
/* width of bitfield data_tc{t}_credit_max[f:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_WIDTH 16
|
||||
/* default value of bitfield data_tc{t}_credit_max[f:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTCREDIT_MAX_DEFAULT 0x0
|
||||
|
||||
/* tx data_tc{t}_weight[8:0] bitfield definitions
|
||||
* preprocessor definitions for the bitfield "data_tc{t}_weight[8:0]".
|
||||
/* tx data_tc{t}_weight[e:0] bitfield definitions
|
||||
* preprocessor definitions for the bitfield "data_tc{t}_weight[e:0]".
|
||||
* parameter: tc {t} | stride size 0x4 | range [0, 7]
|
||||
* port="pif_tps_data_tc0_weight_i[8:0]"
|
||||
* port="pif_tps_data_tc0_weight_i[14:0]"
|
||||
*/
|
||||
|
||||
/* register address for bitfield data_tc{t}_weight[8:0] */
|
||||
/* register address for bitfield data_tc{t}_weight[e:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTWEIGHT_ADR(tc) (0x00007110 + (tc) * 0x4)
|
||||
/* bitmask for bitfield data_tc{t}_weight[8:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTWEIGHT_MSK 0x000001ff
|
||||
/* inverted bitmask for bitfield data_tc{t}_weight[8:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTWEIGHT_MSKN 0xfffffe00
|
||||
/* lower bit position of bitfield data_tc{t}_weight[8:0] */
|
||||
/* bitmask for bitfield data_tc{t}_weight[e:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTWEIGHT_MSK 0x00007fff
|
||||
/* inverted bitmask for bitfield data_tc{t}_weight[e:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTWEIGHT_MSKN 0xffff8000
|
||||
/* lower bit position of bitfield data_tc{t}_weight[e:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTWEIGHT_SHIFT 0
|
||||
/* width of bitfield data_tc{t}_weight[8:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTWEIGHT_WIDTH 9
|
||||
/* default value of bitfield data_tc{t}_weight[8:0] */
|
||||
/* width of bitfield data_tc{t}_weight[e:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTWEIGHT_WIDTH 15
|
||||
/* default value of bitfield data_tc{t}_weight[e:0] */
|
||||
#define HW_ATL2_TPS_DATA_TCTWEIGHT_DEFAULT 0x0
|
||||
|
||||
/* tx interrupt moderation control register definitions
|
||||
|
||||
Loading…
Reference in New Issue
Block a user