mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-14 23:36:45 +07:00
bnx2x: Semantic renovation
Mostly corrects white spaces, indentations, and comments. Signed-off-by: Yuval Mintz <yuvalmin@broadcom.com> Signed-off-by: Ariel Elior <ariele@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Yuval Mintz
David S. Miller
parent
f5ae62799a
commit
2de67439c1
@ -141,8 +141,8 @@ do { \
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#define bnx2x_mc_addr(ha) ((ha)->addr)
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#define bnx2x_uc_addr(ha) ((ha)->addr)
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#define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
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#define U64_HI(x) (u32)(((u64)(x)) >> 32)
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#define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff))
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#define U64_HI(x) ((u32)(((u64)(x)) >> 32))
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#define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
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@ -812,7 +812,7 @@ struct bnx2x_common {
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#define CHIP_NUM_57811 0x163d
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#define CHIP_NUM_57811_MF 0x163e
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#define CHIP_NUM_57811_VF 0x163f
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#define CHIP_NUM_57840_OBSOLETE 0x168d
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#define CHIP_NUM_57840_OBSOLETE 0x168d
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#define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
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#define CHIP_NUM_57840_4_10 0x16a1
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#define CHIP_NUM_57840_2_20 0x16a2
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@ -1195,11 +1195,11 @@ struct bnx2x_fw_stats_req {
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};
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struct bnx2x_fw_stats_data {
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struct stats_counter storm_counters;
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struct per_port_stats port;
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struct per_pf_stats pf;
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struct stats_counter storm_counters;
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struct per_port_stats port;
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struct per_pf_stats pf;
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struct fcoe_statistics_params fcoe;
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struct per_queue_stats queue_stats[1];
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struct per_queue_stats queue_stats[1];
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};
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/* Public slow path states */
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@ -1343,8 +1343,6 @@ struct bnx2x {
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__le16 *eq_cons_sb;
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atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
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/* Counter for marking that there is a STAT_QUERY ramrod pending */
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u16 stats_pending;
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/* Counter for completed statistics ramrods */
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@ -2076,10 +2074,8 @@ void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
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#define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
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BNX2X_PHY_LOOPBACK_FAILED)
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#define STROM_ASSERT_ARRAY_SIZE 50
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/* must be used on a CID before placing it on a HW ring */
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#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
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(BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
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@ -2110,7 +2106,6 @@ void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
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/* Memory of fairness algorithm . 2 cycles */
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#define FAIR_MEM 2
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#define ATTN_NIG_FOR_FUNC (1L << 8)
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#define ATTN_SW_TIMER_4_FUNC (1L << 9)
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#define GPIO_2_FUNC (1L << 10)
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@ -2215,7 +2210,6 @@ void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
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#define MULTI_MASK 0x7f
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#define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
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#define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
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#define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
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@ -2243,18 +2237,6 @@ void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
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(&bp->def_status_blk->sp_sb.\
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index_values[HC_SP_INDEX_ETH_DEF_CONS])
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#define SET_FLAG(value, mask, flag) \
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do {\
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(value) &= ~(mask);\
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(value) |= ((flag) << (mask##_SHIFT));\
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} while (0)
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#define GET_FLAG(value, mask) \
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(((value) & (mask)) >> (mask##_SHIFT))
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#define GET_FIELD(value, fname) \
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(((value) & (fname##_MASK)) >> (fname##_SHIFT))
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#define CAM_IS_INVALID(x) \
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(GET_FLAG(x.flags, \
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MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
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@ -2265,7 +2247,6 @@ void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
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#define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
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TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
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#ifndef PXP2_REG_PXP2_INT_STS
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#define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
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#endif
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@ -2285,8 +2266,8 @@ void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
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(!((me_reg) & ME_REG_VF_ERR)))
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int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code);
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/* Congestion management fairness mode */
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#define CMNG_FNS_NONE 0
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#define CMNG_FNS_MINMAX 1
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#define CMNG_FNS_NONE 0
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#define CMNG_FNS_MINMAX 1
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#define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
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#define HC_SEG_ACCESS_ATTN 4
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@ -2302,7 +2283,6 @@ static const u32 dmae_reg_go_c[] = {
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void bnx2x_set_ethtool_ops(struct net_device *netdev);
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void bnx2x_notify_link_changed(struct bnx2x *bp);
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#define BNX2X_MF_SD_PROTOCOL(bp) \
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((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
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@ -2323,6 +2303,18 @@ void bnx2x_notify_link_changed(struct bnx2x *bp);
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(BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
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BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
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#define SET_FLAG(value, mask, flag) \
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do {\
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(value) &= ~(mask);\
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(value) |= ((flag) << (mask##_SHIFT));\
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} while (0)
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#define GET_FLAG(value, mask) \
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(((value) & (mask)) >> (mask##_SHIFT))
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#define GET_FIELD(value, fname) \
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(((value) & (fname##_MASK)) >> (fname##_SHIFT))
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enum {
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SWITCH_UPDATE,
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AFEX_UPDATE,
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@ -237,7 +237,7 @@ int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata)
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txdata->txq_index, hw_cons, sw_cons, pkt_cons);
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bd_cons = bnx2x_free_tx_pkt(bp, txdata, pkt_cons,
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&pkts_compl, &bytes_compl);
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&pkts_compl, &bytes_compl);
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sw_cons++;
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}
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@ -343,14 +343,14 @@ static inline void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
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fp->last_max_sge, fp->rx_sge_prod);
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}
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/* Set Toeplitz hash value in the skb using the value from the
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/* Get Toeplitz hash value in the skb using the value from the
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* CQE (calculated by HW).
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*/
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static u32 bnx2x_get_rxhash(const struct bnx2x *bp,
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const struct eth_fast_path_rx_cqe *cqe,
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bool *l4_rxhash)
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{
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/* Set Toeplitz hash from CQE */
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/* Get Toeplitz hash from CQE */
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if ((bp->dev->features & NETIF_F_RXHASH) &&
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(cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG)) {
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enum eth_rss_hash_type htype;
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@ -449,7 +449,7 @@ static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
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*
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* Approximate value of the MSS for this aggregation calculated using
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* the first packet of it.
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* Compute number of aggregated segments, and gso_type
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* Compute number of aggregated segments, and gso_type.
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*/
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static void bnx2x_set_gro_params(struct sk_buff *skb, u16 parsing_flags,
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u16 len_on_bd, unsigned int pkt_len)
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@ -619,7 +619,6 @@ static void *bnx2x_frag_alloc(const struct bnx2x_fastpath *fp)
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return kmalloc(fp->rx_buf_size + NET_SKB_PAD, GFP_ATOMIC);
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}
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#ifdef CONFIG_INET
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static void bnx2x_gro_ip_csum(struct bnx2x *bp, struct sk_buff *skb)
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{
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@ -1827,7 +1826,6 @@ u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb)
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return __skb_tx_hash(dev, skb, BNX2X_NUM_ETH_QUEUES(bp));
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}
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void bnx2x_set_num_queues(struct bnx2x *bp)
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{
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/* RSS queues */
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@ -2483,7 +2481,6 @@ int bnx2x_load_cnic(struct bnx2x *bp)
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#endif /* ! BNX2X_STOP_ON_ERROR */
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}
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/* must be called with rtnl_lock */
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int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
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{
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@ -3064,7 +3061,6 @@ int bnx2x_poll(struct napi_struct *napi, int budget)
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if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
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bnx2x_tx_int(bp, fp->txdata_ptr[cos]);
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if (bnx2x_has_rx_work(fp)) {
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work_done += bnx2x_rx_int(fp, budget - work_done);
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@ -3337,12 +3333,12 @@ static inline void bnx2x_set_pbd_gso(struct sk_buff *skb,
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* 57712 related
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*/
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static inline u8 bnx2x_set_pbd_csum_e2(struct bnx2x *bp, struct sk_buff *skb,
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u32 *parsing_data, u32 xmit_type)
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u32 *parsing_data, u32 xmit_type)
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{
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*parsing_data |=
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((((u8 *)skb_transport_header(skb) - skb->data) >> 1) <<
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ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT) &
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ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W;
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((((u8 *)skb_transport_header(skb) - skb->data) >> 1) <<
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ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT) &
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ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W;
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if (xmit_type & XMIT_CSUM_TCP) {
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*parsing_data |= ((tcp_hdrlen(skb) / 4) <<
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@ -3488,8 +3484,8 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
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dev_kfree_skb(skb);
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return NETDEV_TX_OK;
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}
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bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++;
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netif_tx_stop_queue(txq);
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bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++;
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netif_tx_stop_queue(txq);
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BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
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return NETDEV_TX_BUSY;
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@ -4254,7 +4250,7 @@ int bnx2x_alloc_mem_bp(struct bnx2x *bp)
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/*
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* The biggest MSI-X table we might need is as a maximum number of fast
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* path IGU SBs plus default SB (for PF).
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* path IGU SBs plus default SB (for PF only).
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*/
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msix_table_size = bp->igu_sb_cnt;
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if (IS_PF(bp))
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@ -4364,7 +4360,7 @@ int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
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{
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u32 sel_phy_idx = bnx2x_get_cur_phy_idx(bp);
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/*
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* The selected actived PHY is always after swapping (in case PHY
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* The selected activated PHY is always after swapping (in case PHY
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* swapping is enabled). So when swapping is enabled, we need to reverse
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* the configuration
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*/
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@ -975,7 +975,6 @@ static inline int bnx2x_func_start(struct bnx2x *bp)
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return bnx2x_func_state_change(bp, &func_params);
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}
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/**
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* bnx2x_set_fw_mac_addr - fill in a MAC address in FW format
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*
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@ -1391,7 +1390,7 @@ static inline bool bnx2x_is_valid_ether_addr(struct bnx2x *bp, u8 *addr)
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}
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/**
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* bnx2x_fill_fw_str - Fill buffer with FW version string.
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* bnx2x_fill_fw_str - Fill buffer with FW version string
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*
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* @bp: driver handle
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* @buf: character buffer to fill with the fw name
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@ -416,6 +416,7 @@ static void bnx2x_pfc_set_pfc(struct bnx2x *bp)
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int mfw_configured = SHMEM2_HAS(bp, drv_flags) &&
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GET_FLAGS(SHMEM2_RD(bp, drv_flags),
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1 << DRV_FLAGS_DCB_MFW_CONFIGURED);
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if (bp->dcbx_port_params.pfc.enabled &&
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(!(bp->dcbx_error & DCBX_REMOTE_MIB_ERROR) || mfw_configured))
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/*
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@ -558,6 +559,7 @@ static void bnx2x_dcbx_update_ets_params(struct bnx2x *bp)
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int mfw_configured = SHMEM2_HAS(bp, drv_flags) &&
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GET_FLAGS(SHMEM2_RD(bp, drv_flags),
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1 << DRV_FLAGS_DCB_MFW_CONFIGURED);
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bnx2x_ets_disabled(&bp->link_params, &bp->link_vars);
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if (!bp->dcbx_port_params.ets.enabled ||
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@ -1904,11 +1906,13 @@ static u8 bnx2x_dcbnl_set_state(struct net_device *netdev, u8 state)
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struct bnx2x *bp = netdev_priv(netdev);
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DP(BNX2X_MSG_DCB, "state = %s\n", state ? "on" : "off");
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/* Fail to set state to "enabled" if dcbx is disabled in nvram */
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if (state && ((bp->dcbx_enabled == BNX2X_DCBX_ENABLED_OFF) ||
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(bp->dcbx_enabled == BNX2X_DCBX_ENABLED_INVALID))) {
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DP(BNX2X_MSG_DCB, "Can not set dcbx to enabled while it is disabled in nvm\n");
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return 1;
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}
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bnx2x_dcbx_set_state(bp, (state ? true : false), bp->dcbx_enabled);
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return 0;
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}
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@ -2052,7 +2056,6 @@ static void bnx2x_dcbnl_set_pfc_cfg(struct net_device *netdev, int prio,
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if (!bnx2x_dcbnl_set_valid(bp) || prio >= MAX_PFC_PRIORITIES)
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return;
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if (setting) {
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bp->dcbx_config_params.admin_pfc_bitmap |= (1 << prio);
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bp->dcbx_config_params.admin_pfc_tx_enable = 1;
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@ -234,7 +234,7 @@ static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
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if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
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!(bp->flags & MF_FUNC_DIS)) {
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cmd->duplex = bp->link_vars.duplex;
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cmd->duplex = bp->link_vars.duplex;
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if (IS_MF(bp) && !BP_NOMCP(bp))
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ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
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@ -400,7 +400,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
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DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
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return -EINVAL;
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}
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/* Save new config in case command complete successully */
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/* Save new config in case command complete successfully */
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new_multi_phy_config = bp->link_params.multi_phy_config;
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/* Get the new cfg_idx */
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cfg_idx = bnx2x_get_link_cfg_idx(bp);
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@ -751,11 +751,10 @@ static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
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* @bp device handle
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* @p output buffer
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*
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* Reads "paged" memories: memories that may only be read by
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* first writing to a specific address ("write address") and
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* then reading from a specific address ("read address"). There
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* may be more than one write address per "page" and more than
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* one read address per write address.
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* Reads "paged" memories: memories that may only be read by first writing to a
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* specific address ("write address") and then reading from a specific address
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* ("read address"). There may be more than one write address per "page" and
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* more than one read address per write address.
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*/
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static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
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{
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@ -1082,13 +1081,13 @@ static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
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struct bnx2x *bp = netdev_priv(dev);
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if (wol->wolopts & ~WAKE_MAGIC) {
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DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
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DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
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return -EINVAL;
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}
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if (wol->wolopts & WAKE_MAGIC) {
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if (bp->flags & NO_WOL_FLAG) {
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DP(BNX2X_MSG_ETHTOOL, "WOL not supproted\n");
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DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
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return -EINVAL;
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}
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bp->wol = 1;
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@ -1161,7 +1160,7 @@ static int bnx2x_get_eeprom_len(struct net_device *dev)
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* Pf B takes the lock and proceeds to perform it's own access.
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* pf A unlocks the per port lock, while pf B is still working (!).
|
||||
* mcp takes the per port lock and corrupts pf B's access (and/or has it's own
|
||||
* acess corrupted by pf B).*
|
||||
* access corrupted by pf B)
|
||||
*/
|
||||
static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
|
||||
{
|
||||
@ -1970,7 +1969,6 @@ static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
enum {
|
||||
BNX2X_CHIP_E1_OFST = 0,
|
||||
BNX2X_CHIP_E1H_OFST,
|
||||
@ -2621,6 +2619,7 @@ static void bnx2x_self_test(struct net_device *dev,
|
||||
etest->flags |= ETH_TEST_FL_FAILED;
|
||||
return;
|
||||
}
|
||||
|
||||
DP(BNX2X_MSG_ETHTOOL,
|
||||
"Self-test command parameters: offline = %d, external_lb = %d\n",
|
||||
(etest->flags & ETH_TEST_FL_OFFLINE),
|
||||
@ -2976,15 +2975,14 @@ static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
|
||||
DP(BNX2X_MSG_ETHTOOL,
|
||||
"Command parameters not supported\n");
|
||||
return -EINVAL;
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
return 0;
|
||||
|
||||
case UDP_V4_FLOW:
|
||||
case UDP_V6_FLOW:
|
||||
/* For UDP either 2-tupple hash or 4-tupple hash is supported */
|
||||
if (info->data == (RXH_IP_SRC | RXH_IP_DST |
|
||||
RXH_L4_B_0_1 | RXH_L4_B_2_3))
|
||||
RXH_L4_B_0_1 | RXH_L4_B_2_3))
|
||||
udp_rss_requested = 1;
|
||||
else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
|
||||
udp_rss_requested = 0;
|
||||
|
||||
@ -305,12 +305,10 @@
|
||||
#define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */
|
||||
#define MAX_VLAN_CREDIT_E2 272 /* Per Path */
|
||||
|
||||
|
||||
/* Maximal aggregation queues supported */
|
||||
#define ETH_MAX_AGGREGATION_QUEUES_E1 32
|
||||
#define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64
|
||||
|
||||
|
||||
#define ETH_NUM_OF_MCAST_BINS 256
|
||||
#define ETH_NUM_OF_MCAST_ENGINES_E2 72
|
||||
|
||||
@ -353,7 +351,6 @@
|
||||
/* max number of slow path commands per port */
|
||||
#define MAX_RAMRODS_PER_PORT 8
|
||||
|
||||
|
||||
/**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
|
||||
|
||||
#define TIMERS_TICK_SIZE_CHIP (1e-3)
|
||||
@ -380,7 +377,6 @@
|
||||
that is not mapped to priority*/
|
||||
#define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF
|
||||
|
||||
|
||||
#define C_ERES_PER_PAGE \
|
||||
(PAGE_SIZE / BITS_TO_BYTES(STRUCT_SIZE(event_ring_elem)))
|
||||
#define C_ERE_PER_PAGE_MASK (C_ERES_PER_PAGE - 1)
|
||||
@ -391,8 +387,6 @@
|
||||
|
||||
#define INVALID_VNIC_ID 0xFF
|
||||
|
||||
|
||||
#define UNDEF_IRO 0x80000000
|
||||
|
||||
|
||||
#endif /* BNX2X_FW_DEFS_H */
|
||||
|
||||
@ -782,12 +782,16 @@ void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
|
||||
printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
|
||||
|
||||
printk("%s", lvl);
|
||||
|
||||
/* dump buffer after the mark */
|
||||
for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
|
||||
for (word = 0; word < 8; word++)
|
||||
data[word] = htonl(REG_RD(bp, offset + 4*word));
|
||||
data[8] = 0x0;
|
||||
pr_cont("%s", (char *)data);
|
||||
}
|
||||
|
||||
/* dump buffer before the mark */
|
||||
for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
|
||||
for (word = 0; word < 8; word++)
|
||||
data[word] = htonl(REG_RD(bp, offset + 4*word));
|
||||
@ -1683,11 +1687,11 @@ static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
|
||||
}
|
||||
|
||||
/**
|
||||
* bnx2x_trylock_leader_lock- try to aquire a leader lock.
|
||||
* bnx2x_trylock_leader_lock- try to acquire a leader lock.
|
||||
*
|
||||
* @bp: driver handle
|
||||
*
|
||||
* Tries to aquire a leader lock for current engine.
|
||||
* Tries to acquire a leader lock for current engine.
|
||||
*/
|
||||
static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
|
||||
{
|
||||
@ -1804,7 +1808,7 @@ void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
|
||||
* mark pending ACK to MCP bit.
|
||||
* prevent case that both bits are cleared.
|
||||
* At the end of load/unload driver checks that
|
||||
* sp_state is cleaerd, and this order prevents
|
||||
* sp_state is cleared, and this order prevents
|
||||
* races
|
||||
*/
|
||||
smp_mb__before_clear_bit();
|
||||
@ -3083,7 +3087,7 @@ static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
|
||||
|
||||
/* Maximum number or simultaneous TPA aggregation for this Queue.
|
||||
*
|
||||
* For PF Clients it should be the maximum avaliable number.
|
||||
* For PF Clients it should be the maximum available number.
|
||||
* VF driver(s) may want to define it to a smaller value.
|
||||
*/
|
||||
rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
|
||||
@ -3796,7 +3800,7 @@ static void bnx2x_fan_failure(struct bnx2x *bp)
|
||||
"Please contact OEM Support for assistance\n");
|
||||
|
||||
/*
|
||||
* Scheudle device reset (unload)
|
||||
* Schedule device reset (unload)
|
||||
* This is due to some boards consuming sufficient power when driver is
|
||||
* up to overheat if fan fails.
|
||||
*/
|
||||
@ -4894,7 +4898,7 @@ static void bnx2x_after_function_update(struct bnx2x *bp)
|
||||
struct bnx2x_queue_update_params *q_update_params =
|
||||
&queue_params.params.update;
|
||||
|
||||
/* Send Q update command with afex vlan removal values for all Qs */
|
||||
/* Send Q update command with afex vlan removal values for all Qs */
|
||||
queue_params.cmd = BNX2X_Q_CMD_UPDATE;
|
||||
|
||||
/* set silent vlan removal values according to vlan mode */
|
||||
@ -4996,7 +5000,6 @@ static void bnx2x_eq_int(struct bnx2x *bp)
|
||||
for (; sw_cons != hw_cons;
|
||||
sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
|
||||
|
||||
|
||||
elem = &bp->eq_ring[EQ_DESC(sw_cons)];
|
||||
|
||||
rc = bnx2x_iov_eq_sp_event(bp, elem);
|
||||
@ -6480,7 +6483,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
|
||||
DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
|
||||
|
||||
/*
|
||||
* take the UNDI lock to protect undi_unload flow from accessing
|
||||
* take the RESET lock to protect undi_unload flow from accessing
|
||||
* registers while we're resetting the chip
|
||||
*/
|
||||
bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
|
||||
@ -6610,7 +6613,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
|
||||
* queues with "old" ILT addresses.
|
||||
* c. PF enable in the PGLC.
|
||||
* d. Clear the was_error of the PF in the PGLC. (could have
|
||||
* occured while driver was down)
|
||||
* occurred while driver was down)
|
||||
* e. PF enable in the CFC (WEAK + STRONG)
|
||||
* f. Timers scan enable
|
||||
* 3. PF driver unload flow:
|
||||
@ -6651,7 +6654,7 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
|
||||
/* Step 1: set zeroes to all ilt page entries with valid bit on
|
||||
* Step 2: set the timers first/last ilt entry to point
|
||||
* to the entire range to prevent ILT range error for 3rd/4th
|
||||
* vnic (this code assumes existance of the vnic)
|
||||
* vnic (this code assumes existence of the vnic)
|
||||
*
|
||||
* both steps performed by call to bnx2x_ilt_client_init_op()
|
||||
* with dummy TM client
|
||||
@ -6668,7 +6671,6 @@ static int bnx2x_init_hw_common(struct bnx2x *bp)
|
||||
REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
|
||||
}
|
||||
|
||||
|
||||
REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
|
||||
REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
|
||||
|
||||
@ -7151,7 +7153,6 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* If SPIO5 is set to generate interrupts, enable it for this port */
|
||||
val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
|
||||
if (val & MISC_SPIO_SPIO5) {
|
||||
@ -8335,8 +8336,8 @@ static void bnx2x_reset_func(struct bnx2x *bp)
|
||||
|
||||
/* SP SB */
|
||||
REG_WR8(bp, BAR_CSTRORM_INTMEM +
|
||||
CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
|
||||
SB_DISABLED);
|
||||
CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
|
||||
SB_DISABLED);
|
||||
|
||||
for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
|
||||
REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
|
||||
@ -9078,8 +9079,7 @@ static int bnx2x_process_kill(struct bnx2x *bp, bool global)
|
||||
int cnt = 1000;
|
||||
u32 val = 0;
|
||||
u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
|
||||
u32 tags_63_32 = 0;
|
||||
|
||||
u32 tags_63_32 = 0;
|
||||
|
||||
/* Empty the Tetris buffer, wait for 1s */
|
||||
do {
|
||||
@ -9974,7 +9974,6 @@ static int bnx2x_prev_unload(struct bnx2x *bp)
|
||||
REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
|
||||
}
|
||||
|
||||
|
||||
do {
|
||||
/* Lock MCP using an unload request */
|
||||
fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
|
||||
@ -10694,21 +10693,21 @@ static void bnx2x_get_fcoe_info(struct bnx2x *bp)
|
||||
/* Port info */
|
||||
bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
|
||||
SHMEM_RD(bp,
|
||||
dev_info.port_hw_config[port].
|
||||
dev_info.port_hw_config[port].
|
||||
fcoe_wwn_port_name_upper);
|
||||
bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
|
||||
SHMEM_RD(bp,
|
||||
dev_info.port_hw_config[port].
|
||||
dev_info.port_hw_config[port].
|
||||
fcoe_wwn_port_name_lower);
|
||||
|
||||
/* Node info */
|
||||
bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
|
||||
SHMEM_RD(bp,
|
||||
dev_info.port_hw_config[port].
|
||||
dev_info.port_hw_config[port].
|
||||
fcoe_wwn_node_name_upper);
|
||||
bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
|
||||
SHMEM_RD(bp,
|
||||
dev_info.port_hw_config[port].
|
||||
dev_info.port_hw_config[port].
|
||||
fcoe_wwn_node_name_lower);
|
||||
} else if (!IS_MF_SD(bp)) {
|
||||
/*
|
||||
@ -11611,7 +11610,6 @@ static int bnx2x_set_mc_list(struct bnx2x *bp)
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
/* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
|
||||
void bnx2x_set_rx_mode(struct net_device *dev)
|
||||
{
|
||||
@ -11899,13 +11897,14 @@ static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
|
||||
* support Physical Device Assignment where kernel BDF maybe arbitrary
|
||||
* (depending on hypervisor).
|
||||
*/
|
||||
if (chip_is_e1x)
|
||||
if (chip_is_e1x) {
|
||||
bp->pf_num = PCI_FUNC(pdev->devfn);
|
||||
else {/* chip is E2/3*/
|
||||
} else {
|
||||
/* chip is E2/3*/
|
||||
pci_read_config_dword(bp->pdev,
|
||||
PCICFG_ME_REGISTER, &pci_cfg_dword);
|
||||
bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
|
||||
ME_REG_ABS_PF_NUM_SHIFT);
|
||||
ME_REG_ABS_PF_NUM_SHIFT);
|
||||
}
|
||||
BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
|
||||
|
||||
@ -12426,7 +12425,7 @@ static int bnx2x_init_one(struct pci_dev *pdev,
|
||||
BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
|
||||
BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
|
||||
BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
|
||||
tx_count, rx_count);
|
||||
tx_count, rx_count);
|
||||
|
||||
rc = bnx2x_init_bp(bp);
|
||||
if (rc)
|
||||
|
||||
@ -1442,7 +1442,7 @@ static int bnx2x_complete_vlan_mac(struct bnx2x *bp,
|
||||
if (cqe->message.error)
|
||||
return -EINVAL;
|
||||
|
||||
/* Run the next bulk of pending commands if requeted */
|
||||
/* Run the next bulk of pending commands if requested */
|
||||
if (test_bit(RAMROD_CONT, ramrod_flags)) {
|
||||
rc = bnx2x_exe_queue_step(bp, &o->exe_queue, ramrod_flags);
|
||||
if (rc < 0)
|
||||
@ -2103,7 +2103,7 @@ static inline void __storm_memset_mac_filters(struct bnx2x *bp,
|
||||
static int bnx2x_set_rx_mode_e1x(struct bnx2x *bp,
|
||||
struct bnx2x_rx_mode_ramrod_params *p)
|
||||
{
|
||||
/* update the bp MAC filter structure */
|
||||
/* update the bp MAC filter structure */
|
||||
u32 mask = (1 << p->cl_id);
|
||||
|
||||
struct tstorm_eth_mac_filter_config *mac_filters =
|
||||
@ -2166,7 +2166,7 @@ static int bnx2x_set_rx_mode_e1x(struct bnx2x *bp,
|
||||
mac_filters->unmatched_unicast & ~mask;
|
||||
|
||||
DP(BNX2X_MSG_SP, "drop_ucast 0x%x\ndrop_mcast 0x%x\n accp_ucast 0x%x\n"
|
||||
"accp_mcast 0x%x\naccp_bcast 0x%x\n",
|
||||
"accp_mcast 0x%x\naccp_bcast 0x%x\n",
|
||||
mac_filters->ucast_drop_all, mac_filters->mcast_drop_all,
|
||||
mac_filters->ucast_accept_all, mac_filters->mcast_accept_all,
|
||||
mac_filters->bcast_accept_all);
|
||||
@ -2790,7 +2790,7 @@ static inline void bnx2x_mcast_hdl_add(struct bnx2x *bp,
|
||||
cnt++;
|
||||
|
||||
DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
|
||||
mlist_pos->mac);
|
||||
mlist_pos->mac);
|
||||
}
|
||||
|
||||
*line_idx = cnt;
|
||||
@ -3085,7 +3085,7 @@ static inline void bnx2x_mcast_hdl_add_e1h(struct bnx2x *bp,
|
||||
BNX2X_57711_SET_MC_FILTER(mc_filter, bit);
|
||||
|
||||
DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC, bin %d\n",
|
||||
mlist_pos->mac, bit);
|
||||
mlist_pos->mac, bit);
|
||||
|
||||
/* bookkeeping... */
|
||||
BIT_VEC64_SET_BIT(o->registry.aprox_match.vec,
|
||||
@ -3319,7 +3319,7 @@ static inline int bnx2x_mcast_handle_restore_cmd_e1(
|
||||
i++;
|
||||
|
||||
DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
|
||||
cfg_data.mac);
|
||||
cfg_data.mac);
|
||||
}
|
||||
|
||||
*rdata_idx = i;
|
||||
@ -3355,7 +3355,7 @@ static inline int bnx2x_mcast_handle_pending_cmds_e1(
|
||||
cnt++;
|
||||
|
||||
DP(BNX2X_MSG_SP, "About to configure %pM mcast MAC\n",
|
||||
pmac_pos->mac);
|
||||
pmac_pos->mac);
|
||||
}
|
||||
break;
|
||||
|
||||
@ -5652,9 +5652,9 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp,
|
||||
memset(rdata, 0, sizeof(*rdata));
|
||||
|
||||
/* Fill the ramrod data with provided parameters */
|
||||
rdata->function_mode = (u8)start_params->mf_mode;
|
||||
rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag);
|
||||
rdata->path_id = BP_PATH(bp);
|
||||
rdata->function_mode = (u8)start_params->mf_mode;
|
||||
rdata->sd_vlan_tag = cpu_to_le16(start_params->sd_vlan_tag);
|
||||
rdata->path_id = BP_PATH(bp);
|
||||
rdata->network_cos_mode = start_params->network_cos_mode;
|
||||
|
||||
/*
|
||||
|
||||
@ -54,7 +54,7 @@ typedef enum {
|
||||
BNX2X_OBJ_TYPE_RX_TX,
|
||||
} bnx2x_obj_type;
|
||||
|
||||
/* Filtering states */
|
||||
/* Public slow path states */
|
||||
enum {
|
||||
BNX2X_FILTER_MAC_PENDING,
|
||||
BNX2X_FILTER_VLAN_PENDING,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user