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ARM: dts: socfpga: Adjust GMAC1 clock and TXD lines skew on VINING FPGA

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Adjust GMAC1 clock lines skew to maximum (+960 ps) and TXD lines skew
to minimum (-420 ps), to improve signal integrity.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
This commit is contained in:
Marek Vasut 2019-06-28 02:19:44 +02:00 committed by Dinh Nguyen
parent 325ec920ee
commit 2dbaa6a6dc
1 changed files with 6 additions and 2 deletions
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8
arch/arm/boot/dts/socfpga_cyclone5_vining_fpga.dts
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@ -96,10 +96,14 @@ phy1: ethernet-phy@1 {
rxd1-skew-ps = <0>;
rxd2-skew-ps = <0>;
rxd3-skew-ps = <0>;
txd0-skew-ps = <0>;
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
txen-skew-ps = <0>;
txc-skew-ps = <2600>;
txc-skew-ps = <1860>;
rxdv-skew-ps = <0>;
rxc-skew-ps = <2000>;
rxc-skew-ps = <1860>;
};
};
};