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mtd: spi-nor: Move Xilinx bits out of core.c

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Create a SPI NOR manufacturer driver for Xilinx chips, and move the
Xilinx definitions outside of core.c.

While at it, remove the SPI_S3AN flag which is now useless.

Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
This commit is contained in:
Boris Brezillon 2020-03-13 19:42:50 +00:00 committed by Tudor Ambarus
parent d825925726
commit 2d47cac1ee
No known key found for this signature in database
GPG Key ID: 4B554F47A58D14E9
4 changed files with 98 additions and 86 deletions
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1
drivers/mtd/spi-nor/Makefile
View File

@ -15,4 +15,5 @@ spi-nor-objs += micron-st.o
spi-nor-objs += spansion.o
spi-nor-objs += sst.o
spi-nor-objs += winbond.o
spi-nor-objs += xilinx.o
obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o

76
drivers/mtd/spi-nor/core.c
View File

@ -1095,26 +1095,6 @@ void spi_nor_unlock_and_unprep(struct spi_nor *nor)
mutex_unlock(&nor->lock);
}
/*
* This code converts an address to the Default Address Mode, that has non
* power of two page sizes. We must support this mode because it is the default
* mode supported by Xilinx tools, it can access the whole flash area and
* changing over to the Power-of-two mode is irreversible and corrupts the
* original data.
* Addr can safely be unsigned int, the biggest S3AN device is smaller than
* 4 MiB.
*/
static u32 s3an_convert_addr(struct spi_nor *nor, u32 addr)
{
u32 offset, page;
offset = addr % nor->page_size;
page = addr / nor->page_size;
page <<= (nor->page_size > 512) ? 10 : 9;
return page | offset;
}
static u32 spi_nor_convert_addr(struct spi_nor *nor, loff_t addr)
{
if (!nor->params.convert_addr)
@ -1963,13 +1943,6 @@ int spi_nor_sr2_bit7_quad_enable(struct spi_nor *nor)
* old entries may be missing 4K flag.
*/
static const struct flash_info spi_nor_ids[] = {
/* Xilinx S3AN Internal Flash */
{ "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
{ "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
{ "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
{ "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
{ "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
/* XMC (Wuhan Xinxin Semiconductor Manufacturing Corp.) */
{ "XM25QH64A", INFO(0x207017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
{ "XM25QH128A", INFO(0x207018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
@ -1992,6 +1965,7 @@ static const struct spi_nor_manufacturer *manufacturers[] = {
&spi_nor_spansion,
&spi_nor_sst,
&spi_nor_winbond,
&spi_nor_xilinx,
};
static const struct flash_info *
@ -2177,46 +2151,6 @@ static int spi_nor_check(struct spi_nor *nor)
return 0;
}
static int s3an_nor_setup(struct spi_nor *nor,
const struct spi_nor_hwcaps *hwcaps)
{
int ret;
ret = spi_nor_xread_sr(nor, nor->bouncebuf);
if (ret)
return ret;
nor->erase_opcode = SPINOR_OP_XSE;
nor->program_opcode = SPINOR_OP_XPP;
nor->read_opcode = SPINOR_OP_READ;
nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
/*
* This flashes have a page size of 264 or 528 bytes (known as
* Default addressing mode). It can be changed to a more standard
* Power of two mode where the page size is 256/512. This comes
* with a price: there is 3% less of space, the data is corrupted
* and the page size cannot be changed back to default addressing
* mode.
*
* The current addressing mode can be read from the XRDSR register
* and should not be changed, because is a destructive operation.
*/
if (nor->bouncebuf[0] & XSR_PAGESIZE) {
/* Flash in Power of 2 mode */
nor->page_size = (nor->page_size == 264) ? 256 : 512;
nor->mtd.writebufsize = nor->page_size;
nor->mtd.size = 8 * nor->page_size * nor->info->n_sectors;
nor->mtd.erasesize = 8 * nor->page_size;
} else {
/* Flash in Default addressing mode */
nor->params.convert_addr = s3an_convert_addr;
nor->mtd.erasesize = nor->info->sector_size;
}
return 0;
}
static void
spi_nor_set_read_settings(struct spi_nor_read_command *read,
u8 num_mode_clocks,
@ -2815,11 +2749,6 @@ static void spi_nor_info_init_params(struct spi_nor *nor)
spi_nor_init_uniform_erase_map(map, erase_mask, params->size);
}
static void s3an_post_sfdp_fixups(struct spi_nor *nor)
{
nor->params.setup = s3an_nor_setup;
}
/**
* spi_nor_post_sfdp_fixups() - Updates the flash's parameters and settings
* after SFDP has been parsed (is also called for SPI NORs that do not
@ -2832,9 +2761,6 @@ static void s3an_post_sfdp_fixups(struct spi_nor *nor)
*/
static void spi_nor_post_sfdp_fixups(struct spi_nor *nor)
{
if (nor->info->flags & SPI_S3AN)
s3an_post_sfdp_fixups(nor);
if (nor->manufacturer && nor->manufacturer->fixups &&
nor->manufacturer->fixups->post_sfdp)
nor->manufacturer->fixups->post_sfdp(nor);

13
drivers/mtd/spi-nor/core.h
View File

@ -73,16 +73,6 @@ struct flash_info {
#define SPI_NOR_XSR_RDY BIT(10) /*
* S3AN flashes have specific opcode to
* read the status register.
* Flags SPI_NOR_XSR_RDY and SPI_S3AN
* use the same bit as one implies the
* other, but we will get rid of
* SPI_S3AN soon.
*/
#define SPI_S3AN BIT(10) /*
* Xilinx Spartan 3AN In-System Flash
* (MFR cannot be used for probing
* because it has the same value as
* ATMEL flashes)
*/
#define SPI_NOR_4B_OPCODES BIT(11) /*
* Use dedicated 4byte address op codes
@ -150,7 +140,7 @@ struct flash_info {
.n_sectors = (_n_sectors), \
.page_size = _page_size, \
.addr_width = 3, \
.flags = SPI_NOR_NO_FR | SPI_S3AN,
.flags = SPI_NOR_NO_FR | SPI_NOR_XSR_RDY,
/**
* struct spi_nor_manufacturer - SPI NOR manufacturer object
@ -182,6 +172,7 @@ extern const struct spi_nor_manufacturer spi_nor_st;
extern const struct spi_nor_manufacturer spi_nor_spansion;
extern const struct spi_nor_manufacturer spi_nor_sst;
extern const struct spi_nor_manufacturer spi_nor_winbond;
extern const struct spi_nor_manufacturer spi_nor_xilinx;
int spi_nor_write_enable(struct spi_nor *nor);
int spi_nor_write_disable(struct spi_nor *nor);

94
drivers/mtd/spi-nor/xilinx.c Normal file
View File

@ -0,0 +1,94 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2005, Intec Automation Inc.
* Copyright (C) 2014, Freescale Semiconductor, Inc.
*/
#include <linux/mtd/spi-nor.h>
#include "core.h"
static const struct flash_info xilinx_parts[] = {
/* Xilinx S3AN Internal Flash */
{ "3S50AN", S3AN_INFO(0x1f2200, 64, 264) },
{ "3S200AN", S3AN_INFO(0x1f2400, 256, 264) },
{ "3S400AN", S3AN_INFO(0x1f2400, 256, 264) },
{ "3S700AN", S3AN_INFO(0x1f2500, 512, 264) },
{ "3S1400AN", S3AN_INFO(0x1f2600, 512, 528) },
};
/*
* This code converts an address to the Default Address Mode, that has non
* power of two page sizes. We must support this mode because it is the default
* mode supported by Xilinx tools, it can access the whole flash area and
* changing over to the Power-of-two mode is irreversible and corrupts the
* original data.
* Addr can safely be unsigned int, the biggest S3AN device is smaller than
* 4 MiB.
*/
static u32 s3an_convert_addr(struct spi_nor *nor, u32 addr)
{
u32 offset, page;
offset = addr % nor->page_size;
page = addr / nor->page_size;
page <<= (nor->page_size > 512) ? 10 : 9;
return page | offset;
}
static int xilinx_nor_setup(struct spi_nor *nor,
const struct spi_nor_hwcaps *hwcaps)
{
int ret;
ret = spi_nor_xread_sr(nor, nor->bouncebuf);
if (ret)
return ret;
nor->erase_opcode = SPINOR_OP_XSE;
nor->program_opcode = SPINOR_OP_XPP;
nor->read_opcode = SPINOR_OP_READ;
nor->flags |= SNOR_F_NO_OP_CHIP_ERASE;
/*
* This flashes have a page size of 264 or 528 bytes (known as
* Default addressing mode). It can be changed to a more standard
* Power of two mode where the page size is 256/512. This comes
* with a price: there is 3% less of space, the data is corrupted
* and the page size cannot be changed back to default addressing
* mode.
*
* The current addressing mode can be read from the XRDSR register
* and should not be changed, because is a destructive operation.
*/
if (nor->bouncebuf[0] & XSR_PAGESIZE) {
/* Flash in Power of 2 mode */
nor->page_size = (nor->page_size == 264) ? 256 : 512;
nor->mtd.writebufsize = nor->page_size;
nor->mtd.size = 8 * nor->page_size * nor->info->n_sectors;
nor->mtd.erasesize = 8 * nor->page_size;
} else {
/* Flash in Default addressing mode */
nor->params.convert_addr = s3an_convert_addr;
nor->mtd.erasesize = nor->info->sector_size;
}
return 0;
}
static void xilinx_post_sfdp_fixups(struct spi_nor *nor)
{
nor->params.setup = xilinx_nor_setup;
}
static const struct spi_nor_fixups xilinx_fixups = {
.post_sfdp = xilinx_post_sfdp_fixups,
};
const struct spi_nor_manufacturer spi_nor_xilinx = {
.name = "xilinx",
.parts = xilinx_parts,
.nparts = ARRAY_SIZE(xilinx_parts),
.fixups = &xilinx_fixups,
};