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usb: gadget: bcm63xx_udc: fix build failure on DMA channel code
Commit 3dc6475
("bcm63xx_enet: add support Broadcom BCM6345 Ethernet")
changed the ENETDMA[CS] macros such that they are no longer macros, but
actual register offset definitions. The bcm63xx_udc driver was not
updated, and as a result, causes the following build error to pop up:
CC drivers/usb/gadget/u_ether.o
drivers/usb/gadget/bcm63xx_udc.c: In function 'iudma_write':
drivers/usb/gadget/bcm63xx_udc.c:642:24: error: called object '0' is not
a function
drivers/usb/gadget/bcm63xx_udc.c: In function 'iudma_reset_channel':
drivers/usb/gadget/bcm63xx_udc.c:698:46: error: called object '0' is not
a function
drivers/usb/gadget/bcm63xx_udc.c:700:49: error: called object '0' is not
a function
Fix this by updating usb_dmac_{read,write}l and usb_dmas_{read,write}l to
take an extra channel argument, and use the channel width
(ENETDMA_CHAN_WIDTH) to offset the register we want to access, hence
doing again what the macro implicitely did for us.
Cc: Kevin Cernekee <cernekee@gmail.com>
Cc: Jonas Gorski <jogo@openwrt.org>
Cc: <stable@vger.kernel.org>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
parent
30d361bf0f
commit
2d1f7af3d6
@ -360,24 +360,30 @@ static inline void usb_dma_writel(struct bcm63xx_udc *udc, u32 val, u32 off)
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bcm_writel(val, udc->iudma_regs + off);
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}
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static inline u32 usb_dmac_readl(struct bcm63xx_udc *udc, u32 off)
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static inline u32 usb_dmac_readl(struct bcm63xx_udc *udc, u32 off, int chan)
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{
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return bcm_readl(udc->iudma_regs + IUDMA_DMAC_OFFSET + off);
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return bcm_readl(udc->iudma_regs + IUDMA_DMAC_OFFSET + off +
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(ENETDMA_CHAN_WIDTH * chan));
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}
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static inline void usb_dmac_writel(struct bcm63xx_udc *udc, u32 val, u32 off)
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static inline void usb_dmac_writel(struct bcm63xx_udc *udc, u32 val, u32 off,
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int chan)
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{
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bcm_writel(val, udc->iudma_regs + IUDMA_DMAC_OFFSET + off);
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bcm_writel(val, udc->iudma_regs + IUDMA_DMAC_OFFSET + off +
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(ENETDMA_CHAN_WIDTH * chan));
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}
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static inline u32 usb_dmas_readl(struct bcm63xx_udc *udc, u32 off)
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static inline u32 usb_dmas_readl(struct bcm63xx_udc *udc, u32 off, int chan)
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{
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return bcm_readl(udc->iudma_regs + IUDMA_DMAS_OFFSET + off);
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return bcm_readl(udc->iudma_regs + IUDMA_DMAS_OFFSET + off +
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(ENETDMA_CHAN_WIDTH * chan));
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}
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static inline void usb_dmas_writel(struct bcm63xx_udc *udc, u32 val, u32 off)
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static inline void usb_dmas_writel(struct bcm63xx_udc *udc, u32 val, u32 off,
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int chan)
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{
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bcm_writel(val, udc->iudma_regs + IUDMA_DMAS_OFFSET + off);
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bcm_writel(val, udc->iudma_regs + IUDMA_DMAS_OFFSET + off +
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(ENETDMA_CHAN_WIDTH * chan));
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}
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static inline void set_clocks(struct bcm63xx_udc *udc, bool is_enabled)
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@ -638,7 +644,7 @@ static void iudma_write(struct bcm63xx_udc *udc, struct iudma_ch *iudma,
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} while (!last_bd);
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usb_dmac_writel(udc, ENETDMAC_CHANCFG_EN_MASK,
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ENETDMAC_CHANCFG_REG(iudma->ch_idx));
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ENETDMAC_CHANCFG_REG, iudma->ch_idx);
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}
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/**
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@ -694,9 +700,9 @@ static void iudma_reset_channel(struct bcm63xx_udc *udc, struct iudma_ch *iudma)
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bcm63xx_fifo_reset_ep(udc, max(0, iudma->ep_num));
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/* stop DMA, then wait for the hardware to wrap up */
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usb_dmac_writel(udc, 0, ENETDMAC_CHANCFG_REG(ch_idx));
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usb_dmac_writel(udc, 0, ENETDMAC_CHANCFG_REG, ch_idx);
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while (usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG(ch_idx)) &
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while (usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG, ch_idx) &
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ENETDMAC_CHANCFG_EN_MASK) {
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udelay(1);
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@ -713,10 +719,10 @@ static void iudma_reset_channel(struct bcm63xx_udc *udc, struct iudma_ch *iudma)
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dev_warn(udc->dev, "forcibly halting IUDMA channel %d\n",
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ch_idx);
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usb_dmac_writel(udc, ENETDMAC_CHANCFG_BUFHALT_MASK,
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ENETDMAC_CHANCFG_REG(ch_idx));
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ENETDMAC_CHANCFG_REG, ch_idx);
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}
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}
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usb_dmac_writel(udc, ~0, ENETDMAC_IR_REG(ch_idx));
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usb_dmac_writel(udc, ~0, ENETDMAC_IR_REG, ch_idx);
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/* don't leave "live" HW-owned entries for the next guy to step on */
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for (d = iudma->bd_ring; d <= iudma->end_bd; d++)
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@ -728,11 +734,11 @@ static void iudma_reset_channel(struct bcm63xx_udc *udc, struct iudma_ch *iudma)
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/* set up IRQs, UBUS burst size, and BD base for this channel */
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usb_dmac_writel(udc, ENETDMAC_IR_BUFDONE_MASK,
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ENETDMAC_IRMASK_REG(ch_idx));
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usb_dmac_writel(udc, 8, ENETDMAC_MAXBURST_REG(ch_idx));
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ENETDMAC_IRMASK_REG, ch_idx);
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usb_dmac_writel(udc, 8, ENETDMAC_MAXBURST_REG, ch_idx);
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usb_dmas_writel(udc, iudma->bd_ring_dma, ENETDMAS_RSTART_REG(ch_idx));
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usb_dmas_writel(udc, 0, ENETDMAS_SRAM2_REG(ch_idx));
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usb_dmas_writel(udc, iudma->bd_ring_dma, ENETDMAS_RSTART_REG, ch_idx);
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usb_dmas_writel(udc, 0, ENETDMAS_SRAM2_REG, ch_idx);
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}
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/**
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@ -2035,7 +2041,7 @@ static irqreturn_t bcm63xx_udc_data_isr(int irq, void *dev_id)
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spin_lock(&udc->lock);
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usb_dmac_writel(udc, ENETDMAC_IR_BUFDONE_MASK,
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ENETDMAC_IR_REG(iudma->ch_idx));
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ENETDMAC_IR_REG, iudma->ch_idx);
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bep = iudma->bep;
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rc = iudma_read(udc, iudma);
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@ -2175,18 +2181,18 @@ static int bcm63xx_iudma_dbg_show(struct seq_file *s, void *p)
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seq_printf(s, " [ep%d]:\n",
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max_t(int, iudma_defaults[ch_idx].ep_num, 0));
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seq_printf(s, " cfg: %08x; irqstat: %08x; irqmask: %08x; maxburst: %08x\n",
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usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG(ch_idx)),
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usb_dmac_readl(udc, ENETDMAC_IR_REG(ch_idx)),
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usb_dmac_readl(udc, ENETDMAC_IRMASK_REG(ch_idx)),
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usb_dmac_readl(udc, ENETDMAC_MAXBURST_REG(ch_idx)));
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usb_dmac_readl(udc, ENETDMAC_CHANCFG_REG, ch_idx),
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usb_dmac_readl(udc, ENETDMAC_IR_REG, ch_idx),
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usb_dmac_readl(udc, ENETDMAC_IRMASK_REG, ch_idx),
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usb_dmac_readl(udc, ENETDMAC_MAXBURST_REG, ch_idx));
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sram2 = usb_dmas_readl(udc, ENETDMAS_SRAM2_REG(ch_idx));
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sram3 = usb_dmas_readl(udc, ENETDMAS_SRAM3_REG(ch_idx));
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sram2 = usb_dmas_readl(udc, ENETDMAS_SRAM2_REG, ch_idx);
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sram3 = usb_dmas_readl(udc, ENETDMAS_SRAM3_REG, ch_idx);
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seq_printf(s, " base: %08x; index: %04x_%04x; desc: %04x_%04x %08x\n",
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usb_dmas_readl(udc, ENETDMAS_RSTART_REG(ch_idx)),
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usb_dmas_readl(udc, ENETDMAS_RSTART_REG, ch_idx),
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sram2 >> 16, sram2 & 0xffff,
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sram3 >> 16, sram3 & 0xffff,
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usb_dmas_readl(udc, ENETDMAS_SRAM4_REG(ch_idx)));
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usb_dmas_readl(udc, ENETDMAS_SRAM4_REG, ch_idx));
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seq_printf(s, " desc: %d/%d used", iudma->n_bds_used,
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iudma->n_bds);
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