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drm/amdgpu/vcn: Add firmware share memory support

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Added firmware share memory support for VCN. Current multiple
queue mode is enabled only.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
James Zhu 2020-03-29 20:00:22 -04:00 committed by Alex Deucher
parent ad9469fb5b
commit 2c68f0e377
2 changed files with 37 additions and 0 deletions
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13
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
View File

@ -182,6 +182,14 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev)
return r; return r;
} }
} }
r = amdgpu_bo_create_kernel(adev, AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)),
PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.inst[i].fw_shared_bo,
&adev->vcn.inst[i].fw_shared_gpu_addr, &adev->vcn.inst[i].fw_shared_cpu_addr);
if (r) {
dev_err(adev->dev, "VCN %d (%d) failed to allocate fimware shared bo\n", i, r);
return r;
}
} }
return 0; return 0;
@ -196,6 +204,11 @@ int amdgpu_vcn_sw_fini(struct amdgpu_device *adev)
for (j = 0; j < adev->vcn.num_vcn_inst; ++j) { for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
if (adev->vcn.harvest_config & (1 << j)) if (adev->vcn.harvest_config & (1 << j))
continue; continue;
amdgpu_bo_free_kernel(&adev->vcn.inst[j].fw_shared_bo,
&adev->vcn.inst[j].fw_shared_gpu_addr,
(void **)&adev->vcn.inst[j].fw_shared_cpu_addr);
if (adev->vcn.indirect_sram) { if (adev->vcn.indirect_sram) {
amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo, amdgpu_bo_free_kernel(&adev->vcn.inst[j].dpg_sram_bo,
&adev->vcn.inst[j].dpg_sram_gpu_addr, &adev->vcn.inst[j].dpg_sram_gpu_addr,

24
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
View File

@ -132,6 +132,13 @@
} \ } \
} while (0) } while (0)
#define AMDGPU_VCN_MULTI_QUEUE_FLAG (1 << 8)
enum fw_queue_mode {
FW_QUEUE_RING_RESET = 1,
FW_QUEUE_DPG_HOLD_OFF = 2,
};
enum engine_status_constants { enum engine_status_constants {
UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON = 0x2AAAA0,
UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON_2_0 = 0xAAAA0,
@ -179,11 +186,14 @@ struct amdgpu_vcn_inst {
struct amdgpu_irq_src irq; struct amdgpu_irq_src irq;
struct amdgpu_vcn_reg external; struct amdgpu_vcn_reg external;
struct amdgpu_bo *dpg_sram_bo; struct amdgpu_bo *dpg_sram_bo;
struct amdgpu_bo *fw_shared_bo;
struct dpg_pause_state pause_state; struct dpg_pause_state pause_state;
void *dpg_sram_cpu_addr; void *dpg_sram_cpu_addr;
uint64_t dpg_sram_gpu_addr; uint64_t dpg_sram_gpu_addr;
uint32_t *dpg_sram_curr_addr; uint32_t *dpg_sram_curr_addr;
atomic_t dpg_enc_submission_cnt; atomic_t dpg_enc_submission_cnt;
void *fw_shared_cpu_addr;
uint64_t fw_shared_gpu_addr;
}; };
struct amdgpu_vcn { struct amdgpu_vcn {
@ -209,6 +219,20 @@ struct amdgpu_vcn {
int inst_idx, struct dpg_pause_state *new_state); int inst_idx, struct dpg_pause_state *new_state);
}; };
struct amdgpu_fw_shared_multi_queue {
uint8_t decode_queue_mode;
uint8_t encode_generalpurpose_queue_mode;
uint8_t encode_lowlatency_queue_mode;
uint8_t encode_realtime_queue_mode;
uint8_t padding[4];
};
struct amdgpu_fw_shared {
uint32_t present_flag_0;
uint8_t pad[53];
struct amdgpu_fw_shared_multi_queue multi_queue;
} __attribute__((__packed__));
int amdgpu_vcn_sw_init(struct amdgpu_device *adev); int amdgpu_vcn_sw_init(struct amdgpu_device *adev);
int amdgpu_vcn_sw_fini(struct amdgpu_device *adev); int amdgpu_vcn_sw_fini(struct amdgpu_device *adev);
int amdgpu_vcn_suspend(struct amdgpu_device *adev); int amdgpu_vcn_suspend(struct amdgpu_device *adev);