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drm/amdgpu: refactor smu8_send_msg_to_smc and WARN_ON time out
This patch refactors smu8_send_msg_to_smc_with_parameter() to include smu8_send_msg_to_smc_async() so that all the messages sent to SMU can be profiled and appropriately reported if they fail. Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Shirish S <shirish.s@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -24,6 +24,7 @@
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#include <linux/delay.h>
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#include <linux/gfp.h>
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#include <linux/kernel.h>
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#include <linux/ktime.h>
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#include <linux/slab.h>
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#include <linux/types.h>
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@ -61,9 +62,13 @@ static uint32_t smu8_get_argument(struct pp_hwmgr *hwmgr)
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mmSMU_MP1_SRBM2P_ARG_0);
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}
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static int smu8_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg)
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/* Send a message to the SMC, and wait for its response.*/
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static int smu8_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
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uint16_t msg, uint32_t parameter)
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{
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int result = 0;
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ktime_t t_start;
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s64 elapsed_us;
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if (hwmgr == NULL || hwmgr->device == NULL)
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return -EINVAL;
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@ -74,28 +79,31 @@ static int smu8_send_msg_to_smc_async(struct pp_hwmgr *hwmgr, uint16_t msg)
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/* Read the last message to SMU, to report actual cause */
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uint32_t val = cgs_read_register(hwmgr->device,
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mmSMU_MP1_SRBM2P_MSG_0);
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pr_err("smu8_send_msg_to_smc_async (0x%04x) failed\n", msg);
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pr_err("SMU still servicing msg (0x%04x)\n", val);
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pr_err("%s(0x%04x) aborted; SMU still servicing msg (0x%04x)\n",
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__func__, msg, val);
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return result;
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}
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t_start = ktime_get();
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cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
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cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_RESP_0, 0);
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cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_MSG_0, msg);
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return 0;
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result = PHM_WAIT_FIELD_UNEQUAL(hwmgr,
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SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
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elapsed_us = ktime_us_delta(ktime_get(), t_start);
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WARN(result, "%s(0x%04x, %#x) timed out after %lld us\n",
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__func__, msg, parameter, elapsed_us);
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return result;
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}
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/* Send a message to the SMC, and wait for its response.*/
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static int smu8_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg)
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{
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int result = 0;
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result = smu8_send_msg_to_smc_async(hwmgr, msg);
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if (result != 0)
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return result;
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return PHM_WAIT_FIELD_UNEQUAL(hwmgr,
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SMU_MP1_SRBM2P_RESP_0, CONTENT, 0);
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return smu8_send_msg_to_smc_with_parameter(hwmgr, msg, 0);
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}
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static int smu8_set_smc_sram_address(struct pp_hwmgr *hwmgr,
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@ -135,17 +143,6 @@ static int smu8_write_smc_sram_dword(struct pp_hwmgr *hwmgr,
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return result;
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}
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static int smu8_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr,
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uint16_t msg, uint32_t parameter)
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{
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if (hwmgr == NULL || hwmgr->device == NULL)
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return -EINVAL;
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cgs_write_register(hwmgr->device, mmSMU_MP1_SRBM2P_ARG_0, parameter);
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return smu8_send_msg_to_smc(hwmgr, msg);
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}
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static int smu8_check_fw_load_finish(struct pp_hwmgr *hwmgr,
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uint32_t firmware)
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{
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