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drm/i915: fix Haswell pfit power well check v2

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We can't read the pfit regs if the power well is off, so use the cached
value.

v2: re-add lost comment (Jesse)
    make sure the crtc using the fitter is actually enabled (Jesse)

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[danvet: Drop now unused dev_priv, as spotted by Mika.]
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Jesse Barnes 2013-05-02 15:30:47 -07:00 committed by Daniel Vetter
parent 168f836602
commit 2b87f3b1ba
1 changed files with 1 additions and 2 deletions
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3
drivers/gpu/drm/i915/intel_display.c
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@ -5906,7 +5906,6 @@ static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
static void haswell_modeset_global_resources(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
bool enable = false;
struct intel_crtc *crtc;
struct intel_encoder *encoder;
@ -5918,7 +5917,7 @@ static void haswell_modeset_global_resources(struct drm_device *dev)
* sequence that's not yet available. Just in case desktop eDP
* on PORT D is possible on haswell, too. */
/* Even the eDP panel fitter is outside the always-on well. */
if (I915_READ(PF_WIN_SZ(crtc->pipe)))
if (crtc->config.pch_pfit.size && crtc->base.enabled)
enable = true;
}