diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt
index 4fa9539070cb..8ab2d468dbdb 100644
--- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt
+++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm4708-pinmux.txt
@@ -7,13 +7,15 @@ configure controller correctly.
 
 A list of pins varies across chipsets so few bindings are available.
 
+Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon"
+noce.
+
 Required properties:
 - compatible: must be one of:
 	"brcm,bcm4708-pinmux"
 	"brcm,bcm4709-pinmux"
 	"brcm,bcm53012-pinmux"
-- reg: iomem address range of CRU (Central Resource Unit) pin registers
-- reg-names: "cru_gpio_control" - the only needed & supported reg right now
+- offset: offset of pin registers in the CRU block
 
 Functions and their groups available for all chipsets:
 - "spi": "spi_grp"
@@ -37,16 +39,12 @@ Example:
 		#size-cells = <1>;
 
 		cru@100 {
-			compatible = "simple-bus";
+			compatible = "syscon", "simple-mfd";
 			reg = <0x100 0x1a4>;
-			ranges;
-			#address-cells = <1>;
-			#size-cells = <1>;
 
-			pin-controller@1c0 {
+			pinctrl {
 				compatible = "brcm,bcm4708-pinmux";
-				reg = <0x1c0 0x24>;
-				reg-names = "cru_gpio_control";
+				offset = <0xc0>;
 
 				spi-pins {
 					function = "spi";