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dt-bindings: pinctrl: bcm4708-pinmux: rework binding to use syscon
As pointed by Rob, CRU is a kind of block that can't be guaranteed to have everything exposed as subnodes. It's a set of various registers that aren't tied to any single device. It could be described much more accurately as MFD (Multi-Function Device). Some hardware blocks may indeed want to access a register or two of the CRU which requires describing it as the "syscon". While at it replace exmple node name with the standard "pinctrl" (also pointed out by Rob). Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -7,13 +7,15 @@ configure controller correctly.
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A list of pins varies across chipsets so few bindings are available.
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Node of the pinmux must be nested in the CRU (Central Resource Unit) "syscon"
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noce.
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Required properties:
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- compatible: must be one of:
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"brcm,bcm4708-pinmux"
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"brcm,bcm4709-pinmux"
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"brcm,bcm53012-pinmux"
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- reg: iomem address range of CRU (Central Resource Unit) pin registers
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- reg-names: "cru_gpio_control" - the only needed & supported reg right now
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- offset: offset of pin registers in the CRU block
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Functions and their groups available for all chipsets:
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- "spi": "spi_grp"
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@ -37,16 +39,12 @@ Example:
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#size-cells = <1>;
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cru@100 {
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compatible = "simple-bus";
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compatible = "syscon", "simple-mfd";
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reg = <0x100 0x1a4>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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pin-controller@1c0 {
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pinctrl {
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compatible = "brcm,bcm4708-pinmux";
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reg = <0x1c0 0x24>;
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reg-names = "cru_gpio_control";
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offset = <0xc0>;
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spi-pins {
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function = "spi";
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