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drm/radeon: re-enable PTE/PDE packet for set_page on cayman/TN
PTE/PDE doesn't support a single update (count = 1). We had previously disabled it since it we were hitting that case which let to hangs. The PTE/PDE packet is much more efficient for VM updates where it can be used. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -2079,28 +2079,57 @@ void cayman_vm_set_page(struct radeon_device *rdev,
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}
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}
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} else {
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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if ((flags & RADEON_VM_PAGE_SYSTEM) ||
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(count == 1)) {
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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/* for non-physically contiguous pages (system) */
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ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw);
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ib->ptr[ib->length_dw++] = pe;
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ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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if (flags & RADEON_VM_PAGE_SYSTEM) {
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value = radeon_vm_map_gart(rdev, addr);
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value &= 0xFFFFFFFFFFFFF000ULL;
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} else if (flags & RADEON_VM_PAGE_VALID) {
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value = addr;
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} else {
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value = 0;
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/* for non-physically contiguous pages (system) */
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ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, 0, 0, ndw);
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ib->ptr[ib->length_dw++] = pe;
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ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
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for (; ndw > 0; ndw -= 2, --count, pe += 8) {
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if (flags & RADEON_VM_PAGE_SYSTEM) {
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value = radeon_vm_map_gart(rdev, addr);
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value &= 0xFFFFFFFFFFFFF000ULL;
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} else if (flags & RADEON_VM_PAGE_VALID) {
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value = addr;
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} else {
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value = 0;
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}
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addr += incr;
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value |= r600_flags;
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ib->ptr[ib->length_dw++] = value;
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ib->ptr[ib->length_dw++] = upper_32_bits(value);
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}
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addr += incr;
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value |= r600_flags;
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ib->ptr[ib->length_dw++] = value;
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}
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while (ib->length_dw & 0x7)
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ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0);
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} else {
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while (count) {
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ndw = count * 2;
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if (ndw > 0xFFFFE)
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ndw = 0xFFFFE;
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if (flags & RADEON_VM_PAGE_VALID)
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value = addr;
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else
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value = 0;
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/* for physically contiguous pages (vram) */
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ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw);
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ib->ptr[ib->length_dw++] = pe; /* dst addr */
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ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff;
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ib->ptr[ib->length_dw++] = r600_flags; /* mask */
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ib->ptr[ib->length_dw++] = 0;
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ib->ptr[ib->length_dw++] = value; /* value */
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ib->ptr[ib->length_dw++] = upper_32_bits(value);
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ib->ptr[ib->length_dw++] = incr; /* increment size */
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ib->ptr[ib->length_dw++] = 0;
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pe += ndw * 4;
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addr += (ndw / 2) * incr;
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count -= ndw / 2;
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}
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}
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while (ib->length_dw & 0x7)
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@ -684,6 +684,11 @@
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(((vmid) & 0xF) << 20) | \
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(((n) & 0xFFFFF) << 0))
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#define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \
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(1 << 26) | \
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(1 << 21) | \
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(((n) & 0xFFFFF) << 0))
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/* async DMA Packet types */
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#define DMA_PACKET_WRITE 0x2
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#define DMA_PACKET_COPY 0x3
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