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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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mmc: mediatek: add 64G DRAM DMA support
MT2712 MSDC supports 64G DRAM DMA access, it needs update gpd/bd structure. Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Chaotian Jing
Ulf Hansson
parent
99d02d6cd5
commit
2a9bde19e0
@ -71,6 +71,7 @@
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#define SDC_ADV_CFG0 0x64
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#define EMMC_IOCON 0x7c
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#define SDC_ACMD_RESP 0x80
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#define DMA_SA_H4BIT 0x8c
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#define MSDC_DMA_SA 0x90
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#define MSDC_DMA_CTRL 0x98
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#define MSDC_DMA_CFG 0x9c
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@ -195,6 +196,9 @@
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/* SDC_ADV_CFG0 mask */
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#define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */
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/* DMA_SA_H4BIT mask */
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#define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */
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/* MSDC_DMA_CTRL mask */
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#define MSDC_DMA_CTRL_START (0x1 << 0) /* W */
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#define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */
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@ -228,6 +232,7 @@
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#define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */
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#define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */
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#define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */
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#define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */
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#define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */
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#define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */
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@ -281,6 +286,8 @@ struct mt_gpdma_desc {
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#define GPDMA_DESC_BDP (0x1 << 1)
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#define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
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#define GPDMA_DESC_INT (0x1 << 16)
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#define GPDMA_DESC_NEXT_H4 (0xf << 24)
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#define GPDMA_DESC_PTR_H4 (0xf << 28)
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u32 next;
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u32 ptr;
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u32 gpd_data_len;
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@ -297,6 +304,8 @@ struct mt_bdma_desc {
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#define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
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#define BDMA_DESC_BLKPAD (0x1 << 17)
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#define BDMA_DESC_DWPAD (0x1 << 18)
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#define BDMA_DESC_NEXT_H4 (0xf << 24)
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#define BDMA_DESC_PTR_H4 (0xf << 28)
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u32 next;
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u32 ptr;
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u32 bd_data_len;
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@ -335,6 +344,7 @@ struct mtk_mmc_compatible {
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bool busy_check;
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bool stop_clk_fix;
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bool enhance_rx;
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bool support_64g;
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};
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struct msdc_tune_para {
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@ -404,6 +414,7 @@ static const struct mtk_mmc_compatible mt8135_compat = {
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.busy_check = false,
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.stop_clk_fix = false,
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.enhance_rx = false,
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.support_64g = false,
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};
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static const struct mtk_mmc_compatible mt8173_compat = {
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@ -415,6 +426,7 @@ static const struct mtk_mmc_compatible mt8173_compat = {
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.busy_check = false,
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.stop_clk_fix = false,
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.enhance_rx = false,
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.support_64g = false,
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};
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static const struct mtk_mmc_compatible mt2701_compat = {
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@ -426,6 +438,7 @@ static const struct mtk_mmc_compatible mt2701_compat = {
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.busy_check = false,
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.stop_clk_fix = false,
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.enhance_rx = false,
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.support_64g = false,
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};
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static const struct mtk_mmc_compatible mt2712_compat = {
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@ -437,6 +450,7 @@ static const struct mtk_mmc_compatible mt2712_compat = {
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.busy_check = true,
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.stop_clk_fix = true,
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.enhance_rx = true,
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.support_64g = true,
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};
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static const struct mtk_mmc_compatible mt7622_compat = {
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@ -448,6 +462,7 @@ static const struct mtk_mmc_compatible mt7622_compat = {
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.busy_check = true,
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.stop_clk_fix = true,
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.enhance_rx = true,
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.support_64g = false,
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};
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static const struct of_device_id msdc_of_ids[] = {
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@ -557,7 +572,12 @@ static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
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/* init bd */
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bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
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bd[j].bd_info &= ~BDMA_DESC_DWPAD;
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bd[j].ptr = (u32)dma_address;
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bd[j].ptr = lower_32_bits(dma_address);
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if (host->dev_comp->support_64g) {
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bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
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bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
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<< 28;
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}
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bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
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bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
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@ -576,7 +596,10 @@ static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
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dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
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dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8);
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writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
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writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA);
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if (host->dev_comp->support_64g)
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sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
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upper_32_bits(dma->gpd_addr) & 0xf);
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writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
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}
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static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq)
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@ -1367,6 +1390,9 @@ static void msdc_init_hw(struct msdc_host *host)
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MSDC_PATCH_BIT2_CFGCRCSTS);
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}
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if (host->dev_comp->support_64g)
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sdr_set_bits(host->base + MSDC_PATCH_BIT2,
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MSDC_PB2_SUPPORT_64G);
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if (host->dev_comp->data_tune) {
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sdr_set_bits(host->base + tune_reg,
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MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
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@ -1408,19 +1434,32 @@ static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
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{
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struct mt_gpdma_desc *gpd = dma->gpd;
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struct mt_bdma_desc *bd = dma->bd;
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dma_addr_t dma_addr;
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int i;
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memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
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dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
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gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
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gpd->ptr = (u32)dma->bd_addr; /* physical address */
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/* gpd->next is must set for desc DMA
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* That's why must alloc 2 gpd structure.
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*/
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gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc);
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gpd->next = lower_32_bits(dma_addr);
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if (host->dev_comp->support_64g)
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gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
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dma_addr = dma->bd_addr;
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gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
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if (host->dev_comp->support_64g)
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gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
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memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
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for (i = 0; i < (MAX_BD_NUM - 1); i++)
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bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1);
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for (i = 0; i < (MAX_BD_NUM - 1); i++) {
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dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
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bd[i].next = lower_32_bits(dma_addr);
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if (host->dev_comp->support_64g)
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bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
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}
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}
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static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
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@ -1913,7 +1952,10 @@ static int msdc_drv_probe(struct platform_device *pdev)
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mmc->max_blk_size = 2048;
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mmc->max_req_size = 512 * 1024;
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mmc->max_blk_count = mmc->max_req_size / 512;
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host->dma_mask = DMA_BIT_MASK(32);
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if (host->dev_comp->support_64g)
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host->dma_mask = DMA_BIT_MASK(36);
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else
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host->dma_mask = DMA_BIT_MASK(32);
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mmc_dev(mmc)->dma_mask = &host->dma_mask;
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host->timeout_clks = 3 * 1048576;
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