mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 10:56:44 +07:00
mtd: nand/fsmc: Remove sparse warnings and errors
This patch removes the sparse below warnings and errors for nand/fsmc driver /root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31: warning: incorrect type in initializer (different address spaces) /root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31: expected struct fsmc_regs *regs /root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31: got void [noderef] <asn:2>*regs_va [...] Signed-off-by: Vipin Kumar <vipin.kumar@st.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
Vipin Kumar
David Woodhouse
parent
4774fb0a48
commit
2a5dbead29
@ -360,28 +360,29 @@ static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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struct nand_chip *this = mtd->priv;
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struct fsmc_nand_data *host = container_of(mtd,
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struct fsmc_nand_data, mtd);
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struct fsmc_regs *regs = host->regs_va;
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void *__iomem *regs = host->regs_va;
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unsigned int bank = host->bank;
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if (ctrl & NAND_CTRL_CHANGE) {
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u32 pc;
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if (ctrl & NAND_CLE) {
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this->IO_ADDR_R = (void __iomem *)host->cmd_va;
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this->IO_ADDR_W = (void __iomem *)host->cmd_va;
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this->IO_ADDR_R = host->cmd_va;
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this->IO_ADDR_W = host->cmd_va;
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} else if (ctrl & NAND_ALE) {
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this->IO_ADDR_R = (void __iomem *)host->addr_va;
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this->IO_ADDR_W = (void __iomem *)host->addr_va;
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this->IO_ADDR_R = host->addr_va;
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this->IO_ADDR_W = host->addr_va;
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} else {
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this->IO_ADDR_R = (void __iomem *)host->data_va;
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this->IO_ADDR_W = (void __iomem *)host->data_va;
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this->IO_ADDR_R = host->data_va;
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this->IO_ADDR_W = host->data_va;
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}
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if (ctrl & NAND_NCE) {
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writel(readl(®s->bank_regs[bank].pc) | FSMC_ENABLE,
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®s->bank_regs[bank].pc);
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} else {
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writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ENABLE,
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®s->bank_regs[bank].pc);
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}
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pc = readl(FSMC_NAND_REG(regs, bank, PC));
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if (ctrl & NAND_NCE)
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pc |= FSMC_ENABLE;
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else
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pc &= ~FSMC_ENABLE;
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writel(pc, FSMC_NAND_REG(regs, bank, PC));
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}
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mb();
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@ -396,7 +397,7 @@ static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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* This routine initializes timing parameters related to NAND memory access in
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* FSMC registers
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*/
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static void fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank,
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static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
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uint32_t busw, struct fsmc_nand_timings *timings)
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{
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uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
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@ -424,14 +425,14 @@ static void fsmc_nand_setup(struct fsmc_regs *regs, uint32_t bank,
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tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
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if (busw)
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writel(value | FSMC_DEVWID_16, ®s->bank_regs[bank].pc);
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writel(value | FSMC_DEVWID_16, FSMC_NAND_REG(regs, bank, PC));
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else
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writel(value | FSMC_DEVWID_8, ®s->bank_regs[bank].pc);
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writel(value | FSMC_DEVWID_8, FSMC_NAND_REG(regs, bank, PC));
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writel(readl(®s->bank_regs[bank].pc) | tclr | tar,
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®s->bank_regs[bank].pc);
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writel(thiz | thold | twait | tset, ®s->bank_regs[bank].comm);
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writel(thiz | thold | twait | tset, ®s->bank_regs[bank].attrib);
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writel(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
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FSMC_NAND_REG(regs, bank, PC));
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writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, COMM));
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writel(thiz | thold | twait | tset, FSMC_NAND_REG(regs, bank, ATTRIB));
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}
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/*
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@ -441,15 +442,15 @@ static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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struct fsmc_nand_data *host = container_of(mtd,
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struct fsmc_nand_data, mtd);
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struct fsmc_regs *regs = host->regs_va;
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void __iomem *regs = host->regs_va;
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uint32_t bank = host->bank;
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writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCPLEN_256,
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®s->bank_regs[bank].pc);
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writel(readl(®s->bank_regs[bank].pc) & ~FSMC_ECCEN,
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®s->bank_regs[bank].pc);
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writel(readl(®s->bank_regs[bank].pc) | FSMC_ECCEN,
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®s->bank_regs[bank].pc);
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writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
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FSMC_NAND_REG(regs, bank, PC));
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writel(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
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FSMC_NAND_REG(regs, bank, PC));
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writel(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
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FSMC_NAND_REG(regs, bank, PC));
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}
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/*
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@ -462,13 +463,13 @@ static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
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{
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struct fsmc_nand_data *host = container_of(mtd,
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struct fsmc_nand_data, mtd);
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struct fsmc_regs *regs = host->regs_va;
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void __iomem *regs = host->regs_va;
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uint32_t bank = host->bank;
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uint32_t ecc_tmp;
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unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
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do {
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if (readl(®s->bank_regs[bank].sts) & FSMC_CODE_RDY)
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if (readl(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
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break;
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else
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cond_resched();
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@ -479,25 +480,25 @@ static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
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return -ETIMEDOUT;
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}
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ecc_tmp = readl(®s->bank_regs[bank].ecc1);
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ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));
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ecc[0] = (uint8_t) (ecc_tmp >> 0);
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ecc[1] = (uint8_t) (ecc_tmp >> 8);
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ecc[2] = (uint8_t) (ecc_tmp >> 16);
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ecc[3] = (uint8_t) (ecc_tmp >> 24);
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ecc_tmp = readl(®s->bank_regs[bank].ecc2);
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ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC2));
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ecc[4] = (uint8_t) (ecc_tmp >> 0);
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ecc[5] = (uint8_t) (ecc_tmp >> 8);
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ecc[6] = (uint8_t) (ecc_tmp >> 16);
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ecc[7] = (uint8_t) (ecc_tmp >> 24);
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ecc_tmp = readl(®s->bank_regs[bank].ecc3);
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ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC3));
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ecc[8] = (uint8_t) (ecc_tmp >> 0);
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ecc[9] = (uint8_t) (ecc_tmp >> 8);
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ecc[10] = (uint8_t) (ecc_tmp >> 16);
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ecc[11] = (uint8_t) (ecc_tmp >> 24);
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ecc_tmp = readl(®s->bank_regs[bank].sts);
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ecc_tmp = readl(FSMC_NAND_REG(regs, bank, STS));
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ecc[12] = (uint8_t) (ecc_tmp >> 16);
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return 0;
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@ -513,11 +514,11 @@ static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
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{
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struct fsmc_nand_data *host = container_of(mtd,
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struct fsmc_nand_data, mtd);
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struct fsmc_regs *regs = host->regs_va;
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void __iomem *regs = host->regs_va;
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uint32_t bank = host->bank;
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uint32_t ecc_tmp;
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ecc_tmp = readl(®s->bank_regs[bank].ecc1);
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ecc_tmp = readl(FSMC_NAND_REG(regs, bank, ECC1));
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ecc[0] = (uint8_t) (ecc_tmp >> 0);
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ecc[1] = (uint8_t) (ecc_tmp >> 8);
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ecc[2] = (uint8_t) (ecc_tmp >> 16);
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@ -771,13 +772,13 @@ static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
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struct fsmc_nand_data *host = container_of(mtd,
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struct fsmc_nand_data, mtd);
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struct nand_chip *chip = mtd->priv;
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struct fsmc_regs *regs = host->regs_va;
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void __iomem *regs = host->regs_va;
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unsigned int bank = host->bank;
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uint32_t err_idx[8];
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uint32_t num_err, i;
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uint32_t ecc1, ecc2, ecc3, ecc4;
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num_err = (readl(®s->bank_regs[bank].sts) >> 10) & 0xF;
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num_err = (readl(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
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/* no bit flipping */
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if (likely(num_err == 0))
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@ -820,10 +821,10 @@ static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
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* uint64_t array and error offset indexes are populated in err_idx
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* array
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*/
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ecc1 = readl(®s->bank_regs[bank].ecc1);
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ecc2 = readl(®s->bank_regs[bank].ecc2);
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ecc3 = readl(®s->bank_regs[bank].ecc3);
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ecc4 = readl(®s->bank_regs[bank].sts);
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ecc1 = readl(FSMC_NAND_REG(regs, bank, ECC1));
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ecc2 = readl(FSMC_NAND_REG(regs, bank, ECC2));
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ecc3 = readl(FSMC_NAND_REG(regs, bank, ECC3));
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ecc4 = readl(FSMC_NAND_REG(regs, bank, STS));
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err_idx[0] = (ecc1 >> 0) & 0x1FFF;
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err_idx[1] = (ecc1 >> 13) & 0x1FFF;
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@ -863,7 +864,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
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struct fsmc_nand_data *host;
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struct mtd_info *mtd;
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struct nand_chip *nand;
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struct fsmc_regs *regs;
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struct resource *res;
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dma_cap_mask_t mask;
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int ret = 0;
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@ -976,8 +976,6 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
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if (host->mode == USE_DMA_ACCESS)
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init_completion(&host->dma_access_complete);
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regs = host->regs_va;
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/* Link all private pointers */
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mtd = &host->mtd;
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nand = &host->nand;
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@ -1027,7 +1025,8 @@ static int __init fsmc_nand_probe(struct platform_device *pdev)
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break;
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}
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fsmc_nand_setup(regs, host->bank, nand->options & NAND_BUSWIDTH_16,
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fsmc_nand_setup(host->regs_va, host->bank,
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nand->options & NAND_BUSWIDTH_16,
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host->dev_timings);
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if (AMBA_REV_BITS(host->pid) >= 8) {
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@ -32,88 +32,77 @@
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#define FSMC_FLASH_WIDTH8 1
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#define FSMC_FLASH_WIDTH16 2
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struct fsmc_nor_bank_regs {
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uint32_t ctrl;
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uint32_t ctrl_tim;
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};
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/* fsmc controller registers for NOR flash */
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#define CTRL 0x0
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/* ctrl register definitions */
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#define BANK_ENABLE (1 << 0)
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#define MUXED (1 << 1)
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#define NOR_DEV (2 << 2)
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#define WIDTH_8 (0 << 4)
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#define WIDTH_16 (1 << 4)
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#define RSTPWRDWN (1 << 6)
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#define WPROT (1 << 7)
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#define WRT_ENABLE (1 << 12)
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#define WAIT_ENB (1 << 13)
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/* ctrl register definitions */
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#define BANK_ENABLE (1 << 0)
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#define MUXED (1 << 1)
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#define NOR_DEV (2 << 2)
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#define WIDTH_8 (0 << 4)
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#define WIDTH_16 (1 << 4)
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#define RSTPWRDWN (1 << 6)
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#define WPROT (1 << 7)
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#define WRT_ENABLE (1 << 12)
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#define WAIT_ENB (1 << 13)
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/* ctrl_tim register definitions */
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struct fsmc_nand_bank_regs {
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uint32_t pc;
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uint32_t sts;
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uint32_t comm;
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uint32_t attrib;
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uint32_t ioata;
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uint32_t ecc1;
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uint32_t ecc2;
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uint32_t ecc3;
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};
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#define CTRL_TIM 0x4
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/* ctrl_tim register definitions */
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#define FSMC_NOR_BANK_SZ 0x8
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#define FSMC_NOR_REG_SIZE 0x40
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struct fsmc_regs {
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struct fsmc_nor_bank_regs nor_bank_regs[FSMC_MAX_NOR_BANKS];
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uint8_t reserved_1[0x40 - 0x20];
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struct fsmc_nand_bank_regs bank_regs[FSMC_MAX_NAND_BANKS];
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uint8_t reserved_2[0xfe0 - 0xc0];
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uint32_t peripid0; /* 0xfe0 */
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uint32_t peripid1; /* 0xfe4 */
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uint32_t peripid2; /* 0xfe8 */
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uint32_t peripid3; /* 0xfec */
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uint32_t pcellid0; /* 0xff0 */
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uint32_t pcellid1; /* 0xff4 */
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uint32_t pcellid2; /* 0xff8 */
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uint32_t pcellid3; /* 0xffc */
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};
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#define FSMC_NOR_REG(base, bank, reg) (base + \
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FSMC_NOR_BANK_SZ * (bank) + \
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reg)
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/* fsmc controller registers for NAND flash */
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#define PC 0x00
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/* pc register definitions */
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#define FSMC_RESET (1 << 0)
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#define FSMC_WAITON (1 << 1)
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#define FSMC_ENABLE (1 << 2)
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#define FSMC_DEVTYPE_NAND (1 << 3)
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#define FSMC_DEVWID_8 (0 << 4)
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#define FSMC_DEVWID_16 (1 << 4)
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#define FSMC_ECCEN (1 << 6)
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#define FSMC_ECCPLEN_512 (0 << 7)
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#define FSMC_ECCPLEN_256 (1 << 7)
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#define FSMC_TCLR_1 (1)
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#define FSMC_TCLR_SHIFT (9)
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#define FSMC_TCLR_MASK (0xF)
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#define FSMC_TAR_1 (1)
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#define FSMC_TAR_SHIFT (13)
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#define FSMC_TAR_MASK (0xF)
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#define STS 0x04
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/* sts register definitions */
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#define FSMC_CODE_RDY (1 << 15)
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#define COMM 0x08
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/* comm register definitions */
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#define FSMC_TSET_0 0
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#define FSMC_TSET_SHIFT 0
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#define FSMC_TSET_MASK 0xFF
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#define FSMC_TWAIT_6 6
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#define FSMC_TWAIT_SHIFT 8
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#define FSMC_TWAIT_MASK 0xFF
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#define FSMC_THOLD_4 4
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#define FSMC_THOLD_SHIFT 16
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#define FSMC_THOLD_MASK 0xFF
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#define FSMC_THIZ_1 1
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#define FSMC_THIZ_SHIFT 24
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#define FSMC_THIZ_MASK 0xFF
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#define ATTRIB 0x0C
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#define IOATA 0x10
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#define ECC1 0x14
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#define ECC2 0x18
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#define ECC3 0x1C
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#define FSMC_NAND_BANK_SZ 0x20
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#define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
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(FSMC_NAND_BANK_SZ * (bank)) + \
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reg)
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#define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
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/* pc register definitions */
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#define FSMC_RESET (1 << 0)
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#define FSMC_WAITON (1 << 1)
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#define FSMC_ENABLE (1 << 2)
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#define FSMC_DEVTYPE_NAND (1 << 3)
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#define FSMC_DEVWID_8 (0 << 4)
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#define FSMC_DEVWID_16 (1 << 4)
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#define FSMC_ECCEN (1 << 6)
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#define FSMC_ECCPLEN_512 (0 << 7)
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#define FSMC_ECCPLEN_256 (1 << 7)
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#define FSMC_TCLR_1 (1)
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#define FSMC_TCLR_SHIFT (9)
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#define FSMC_TCLR_MASK (0xF)
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#define FSMC_TAR_1 (1)
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#define FSMC_TAR_SHIFT (13)
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#define FSMC_TAR_MASK (0xF)
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/* sts register definitions */
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#define FSMC_CODE_RDY (1 << 15)
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/* comm register definitions */
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#define FSMC_TSET_0 0
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#define FSMC_TSET_SHIFT 0
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#define FSMC_TSET_MASK 0xFF
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#define FSMC_TWAIT_6 6
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#define FSMC_TWAIT_SHIFT 8
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#define FSMC_TWAIT_MASK 0xFF
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||||
#define FSMC_THOLD_4 4
|
||||
#define FSMC_THOLD_SHIFT 16
|
||||
#define FSMC_THOLD_MASK 0xFF
|
||||
#define FSMC_THIZ_1 1
|
||||
#define FSMC_THIZ_SHIFT 24
|
||||
#define FSMC_THIZ_MASK 0xFF
|
||||
|
||||
/*
|
||||
* There are 13 bytes of ecc for every 512 byte block in FSMC version 8
|
||||
* and it has to be read consecutively and immediately after the 512
|
||||
|
||||
Loading…
Reference in New Issue
Block a user