mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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agp: Switch mask_memory() method to take address argument again, not page
In commit 07613ba2
("agp: switch AGP to use page array instead of
unsigned long array") we switched the mask_memory() method to take a
'struct page *' instead of an address. This is painful, because in some
cases it has to be an IOMMU-mapped virtual bus address (in fact,
shouldn't it _always_ be a dma_addr_t returned from pci_map_xxx(), and
we just happen to get lucky most of the time?)
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
This commit is contained in:
parent
ed680c4ad4
commit
2a4ceb6d3e
@ -107,7 +107,7 @@ struct agp_bridge_driver {
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void (*agp_enable)(struct agp_bridge_data *, u32);
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void (*cleanup)(void);
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void (*tlb_flush)(struct agp_memory *);
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unsigned long (*mask_memory)(struct agp_bridge_data *, struct page *, int);
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unsigned long (*mask_memory)(struct agp_bridge_data *, dma_addr_t, int);
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void (*cache_flush)(void);
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int (*create_gatt_table)(struct agp_bridge_data *);
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int (*free_gatt_table)(struct agp_bridge_data *);
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@ -291,7 +291,7 @@ int agp_3_5_enable(struct agp_bridge_data *bridge);
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void global_cache_flush(void);
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void get_agp_version(struct agp_bridge_data *bridge);
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unsigned long agp_generic_mask_memory(struct agp_bridge_data *bridge,
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struct page *page, int type);
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dma_addr_t phys, int type);
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int agp_generic_type_to_mask_type(struct agp_bridge_data *bridge,
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int type);
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struct agp_bridge_data *agp_generic_find_bridge(struct pci_dev *pdev);
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@ -325,7 +325,9 @@ static int amd_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
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addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
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cur_gatt = GET_GATT(addr);
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writel(agp_generic_mask_memory(agp_bridge,
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mem->pages[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
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phys_to_gart(page_to_phys(mem->pages[i])),
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mem->type),
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cur_gatt+GET_GATT_OFF(addr));
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readl(cur_gatt+GET_GATT_OFF(addr)); /* PCI Posting. */
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}
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amd_irongate_tlbflush(mem);
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@ -79,7 +79,8 @@ static int amd64_insert_memory(struct agp_memory *mem, off_t pg_start, int type)
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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tmp = agp_bridge->driver->mask_memory(agp_bridge,
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mem->pages[i], mask_type);
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phys_to_gart(page_to_phys(mem->pages[i])),
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mask_type);
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BUG_ON(tmp & 0xffffff0000000ffcULL);
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pte = (tmp & 0x000000ff00000000ULL) >> 28;
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@ -302,7 +302,8 @@ static int ati_insert_memory(struct agp_memory * mem,
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addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
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cur_gatt = GET_GATT(addr);
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writel(agp_bridge->driver->mask_memory(agp_bridge,
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mem->pages[i], mem->type),
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phys_to_gart(page_to_phys(mem->pages[i])),
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mem->type),
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cur_gatt+GET_GATT_OFF(addr));
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}
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readl(GET_GATT(agp_bridge->gart_bus_addr)); /* PCI posting */
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@ -150,8 +150,8 @@ static int agp_backend_initialize(struct agp_bridge_data *bridge)
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}
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bridge->scratch_page_real = phys_to_gart(page_to_phys(page));
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bridge->scratch_page =
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bridge->driver->mask_memory(bridge, page, 0);
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bridge->scratch_page = bridge->driver->mask_memory(bridge,
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phys_to_gart(page_to_phys(page)), 0);
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}
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size_value = bridge->driver->fetch_size();
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@ -1132,7 +1132,9 @@ int agp_generic_insert_memory(struct agp_memory * mem, off_t pg_start, int type)
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}
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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writel(bridge->driver->mask_memory(bridge, mem->pages[i], mask_type),
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writel(bridge->driver->mask_memory(bridge,
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phys_to_gart(page_to_phys(mem->pages[i])),
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mask_type),
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bridge->gatt_table+j);
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}
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readl(bridge->gatt_table+j-1); /* PCI Posting. */
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@ -1347,9 +1349,8 @@ void global_cache_flush(void)
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EXPORT_SYMBOL(global_cache_flush);
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unsigned long agp_generic_mask_memory(struct agp_bridge_data *bridge,
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struct page *page, int type)
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dma_addr_t addr, int type)
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{
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unsigned long addr = phys_to_gart(page_to_phys(page));
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/* memory type is ignored in the generic routine */
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if (bridge->driver->masks)
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return addr | bridge->driver->masks[0].mask;
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@ -394,10 +394,8 @@ hp_zx1_remove_memory (struct agp_memory *mem, off_t pg_start, int type)
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}
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static unsigned long
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hp_zx1_mask_memory (struct agp_bridge_data *bridge,
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struct page *page, int type)
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hp_zx1_mask_memory (struct agp_bridge_data *bridge, dma_addr_t addr, int type)
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{
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unsigned long addr = phys_to_gart(page_to_phys(page));
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return HP_ZX1_PDIR_VALID_BIT | addr;
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}
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@ -61,7 +61,7 @@
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#define WR_FLUSH_GATT(index) RD_GATT(index)
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static unsigned long i460_mask_memory (struct agp_bridge_data *bridge,
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unsigned long addr, int type);
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dma_addr_t addr, int type);
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static struct {
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void *gatt; /* ioremap'd GATT area */
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@ -546,20 +546,13 @@ static void i460_destroy_page (struct page *page, int flags)
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#endif /* I460_LARGE_IO_PAGES */
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static unsigned long i460_mask_memory (struct agp_bridge_data *bridge,
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unsigned long addr, int type)
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dma_addr_t addr, int type)
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{
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/* Make sure the returned address is a valid GATT entry */
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return bridge->driver->masks[0].mask
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| (((addr & ~((1 << I460_IO_PAGE_SHIFT) - 1)) & 0xfffff000) >> 12);
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}
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static unsigned long i460_page_mask_memory(struct agp_bridge_data *bridge,
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struct page *page, int type)
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{
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unsigned long addr = phys_to_gart(page_to_phys(page));
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return i460_mask_memory(bridge, addr, type);
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}
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const struct agp_bridge_driver intel_i460_driver = {
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.owner = THIS_MODULE,
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.aperture_sizes = i460_sizes,
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@ -569,7 +562,7 @@ const struct agp_bridge_driver intel_i460_driver = {
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.fetch_size = i460_fetch_size,
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.cleanup = i460_cleanup,
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.tlb_flush = i460_tlb_flush,
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.mask_memory = i460_page_mask_memory,
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.mask_memory = i460_mask_memory,
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.masks = i460_masks,
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.agp_enable = agp_generic_enable,
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.cache_flush = global_cache_flush,
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@ -343,7 +343,7 @@ static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
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global_cache_flush();
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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writel(agp_bridge->driver->mask_memory(agp_bridge,
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mem->pages[i],
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phys_to_gart(page_to_phys(mem->pages[i])),
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mask_type),
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intel_private.registers+I810_PTE_BASE+(j*4));
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}
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@ -461,9 +461,8 @@ static void intel_i810_free_by_type(struct agp_memory *curr)
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}
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static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
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struct page *page, int type)
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dma_addr_t addr, int type)
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{
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unsigned long addr = phys_to_gart(page_to_phys(page));
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/* Type checking must be done elsewhere */
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return addr | bridge->driver->masks[type].mask;
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}
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@ -851,7 +850,7 @@ static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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writel(agp_bridge->driver->mask_memory(agp_bridge,
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mem->pages[i], mask_type),
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phys_to_gart(page_to_phys(mem->pages[i])), mask_type),
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intel_private.registers+I810_PTE_BASE+(j*4));
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}
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readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
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@ -1081,7 +1080,9 @@ static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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writel(agp_bridge->driver->mask_memory(agp_bridge,
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mem->pages[i], mask_type), intel_private.gtt+j);
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phys_to_gart(page_to_phys(mem->pages[i])),
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mask_type),
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intel_private.gtt+j);
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}
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readl(intel_private.gtt+j-1);
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@ -1196,9 +1197,8 @@ static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
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* this conditional.
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*/
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static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
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struct page *page, int type)
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dma_addr_t addr, int type)
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{
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dma_addr_t addr = phys_to_gart(page_to_phys(page));
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/* Shift high bits down */
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addr |= (addr >> 28) & 0xf0;
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@ -225,7 +225,7 @@ static int nvidia_insert_memory(struct agp_memory *mem, off_t pg_start, int type
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}
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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writel(agp_bridge->driver->mask_memory(agp_bridge,
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mem->pages[i], mask_type),
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phys_to_gart(page_to_phys(mem->pages[i])), mask_type),
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agp_bridge->gatt_table+nvidia_private.pg_offset+j);
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}
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@ -32,7 +32,7 @@
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#define AGP8X_MODE (1 << AGP8X_MODE_BIT)
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static unsigned long
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parisc_agp_mask_memory(struct agp_bridge_data *bridge, unsigned long addr,
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parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr,
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int type);
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static struct _parisc_agp_info {
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@ -189,20 +189,12 @@ parisc_agp_remove_memory(struct agp_memory *mem, off_t pg_start, int type)
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}
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static unsigned long
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parisc_agp_mask_memory(struct agp_bridge_data *bridge, unsigned long addr,
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parisc_agp_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr,
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int type)
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{
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return SBA_PDIR_VALID_BIT | addr;
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}
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static unsigned long
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parisc_agp_page_mask_memory(struct agp_bridge_data *bridge, struct page *page,
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int type)
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{
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unsigned long addr = phys_to_gart(page_to_phys(page));
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return SBA_PDIR_VALID_BIT | addr;
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}
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static void
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parisc_agp_enable(struct agp_bridge_data *bridge, u32 mode)
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{
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@ -70,10 +70,9 @@ static void sgi_tioca_tlbflush(struct agp_memory *mem)
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* entry.
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*/
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static unsigned long
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sgi_tioca_mask_memory(struct agp_bridge_data *bridge,
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struct page *page, int type)
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sgi_tioca_mask_memory(struct agp_bridge_data *bridge, dma_addr_t addr,
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int type)
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{
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unsigned long addr = phys_to_gart(page_to_phys(page));
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return tioca_physpage_to_gart(addr);
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}
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@ -190,7 +189,8 @@ static int sgi_tioca_insert_memory(struct agp_memory *mem, off_t pg_start,
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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table[j] =
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bridge->driver->mask_memory(bridge, mem->pages[i],
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bridge->driver->mask_memory(bridge,
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phys_to_gart(page_to_phys(mem->pages[i])),
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mem->type);
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}
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@ -349,7 +349,9 @@ static int serverworks_insert_memory(struct agp_memory *mem,
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for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
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addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
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cur_gatt = SVRWRKS_GET_GATT(addr);
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writel(agp_bridge->driver->mask_memory(agp_bridge, mem->pages[i], mem->type), cur_gatt+GET_GATT_OFF(addr));
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writel(agp_bridge->driver->mask_memory(agp_bridge,
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phys_to_gart(page_to_phys(mem->pages[i])), mem->type),
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cur_gatt+GET_GATT_OFF(addr));
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}
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serverworks_tlbflush(mem);
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return 0;
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