mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 10:06:43 +07:00
powerpc/powernv: Drop PHB operation next_error()
The patch drops PHB EEH operation next_error() and merges its logic to eeh_ops::next_error(). Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Gavin Shan
Benjamin Herrenschmidt
parent
40ae5f693f
commit
2a485ad7c8
@ -34,18 +34,6 @@
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#include "powernv.h"
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#include "pci.h"
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static void ioda_eeh_phb_diag(struct eeh_pe *pe)
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{
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struct pnv_phb *phb = pe->phb->private_data;
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long rc;
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rc = opal_pci_get_phb_diag_data2(phb->opal_id, pe->data,
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PNV_PCI_DIAG_BUF_SIZE);
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if (rc != OPAL_SUCCESS)
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pr_warn("%s: Failed to get diag-data for PHB#%x (%ld)\n",
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__func__, pe->phb->global_number, rc);
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}
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static s64 ioda_eeh_phb_poll(struct pnv_phb *phb)
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{
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s64 rc = OPAL_HARDWARE;
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@ -280,345 +268,6 @@ static int ioda_eeh_reset(struct eeh_pe *pe, int option)
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return ret;
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}
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static void ioda_eeh_hub_diag_common(struct OpalIoP7IOCErrorData *data)
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{
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/* GEM */
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if (data->gemXfir || data->gemRfir ||
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data->gemRirqfir || data->gemMask || data->gemRwof)
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pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n",
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be64_to_cpu(data->gemXfir),
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be64_to_cpu(data->gemRfir),
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be64_to_cpu(data->gemRirqfir),
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be64_to_cpu(data->gemMask),
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be64_to_cpu(data->gemRwof));
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/* LEM */
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if (data->lemFir || data->lemErrMask ||
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data->lemAction0 || data->lemAction1 || data->lemWof)
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pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n",
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be64_to_cpu(data->lemFir),
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be64_to_cpu(data->lemErrMask),
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be64_to_cpu(data->lemAction0),
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be64_to_cpu(data->lemAction1),
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be64_to_cpu(data->lemWof));
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}
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static void ioda_eeh_hub_diag(struct pci_controller *hose)
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{
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struct pnv_phb *phb = hose->private_data;
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struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag;
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long rc;
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rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
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if (rc != OPAL_SUCCESS) {
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pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n",
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__func__, phb->hub_id, rc);
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return;
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}
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switch (data->type) {
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case OPAL_P7IOC_DIAG_TYPE_RGC:
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pr_info("P7IOC diag-data for RGC\n\n");
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ioda_eeh_hub_diag_common(data);
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if (data->rgc.rgcStatus || data->rgc.rgcLdcp)
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pr_info(" RGC: %016llx %016llx\n",
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be64_to_cpu(data->rgc.rgcStatus),
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be64_to_cpu(data->rgc.rgcLdcp));
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break;
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case OPAL_P7IOC_DIAG_TYPE_BI:
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pr_info("P7IOC diag-data for BI %s\n\n",
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data->bi.biDownbound ? "Downbound" : "Upbound");
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ioda_eeh_hub_diag_common(data);
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if (data->bi.biLdcp0 || data->bi.biLdcp1 ||
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data->bi.biLdcp2 || data->bi.biFenceStatus)
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pr_info(" BI: %016llx %016llx %016llx %016llx\n",
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be64_to_cpu(data->bi.biLdcp0),
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be64_to_cpu(data->bi.biLdcp1),
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be64_to_cpu(data->bi.biLdcp2),
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be64_to_cpu(data->bi.biFenceStatus));
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break;
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case OPAL_P7IOC_DIAG_TYPE_CI:
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pr_info("P7IOC diag-data for CI Port %d\n\n",
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data->ci.ciPort);
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ioda_eeh_hub_diag_common(data);
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if (data->ci.ciPortStatus || data->ci.ciPortLdcp)
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pr_info(" CI: %016llx %016llx\n",
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be64_to_cpu(data->ci.ciPortStatus),
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be64_to_cpu(data->ci.ciPortLdcp));
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break;
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case OPAL_P7IOC_DIAG_TYPE_MISC:
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pr_info("P7IOC diag-data for MISC\n\n");
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ioda_eeh_hub_diag_common(data);
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break;
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case OPAL_P7IOC_DIAG_TYPE_I2C:
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pr_info("P7IOC diag-data for I2C\n\n");
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ioda_eeh_hub_diag_common(data);
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break;
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default:
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pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n",
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__func__, phb->hub_id, data->type);
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}
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}
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static int ioda_eeh_get_pe(struct pci_controller *hose,
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u16 pe_no, struct eeh_pe **pe)
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{
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struct pnv_phb *phb = hose->private_data;
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struct pnv_ioda_pe *pnv_pe;
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struct eeh_pe *dev_pe;
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struct eeh_dev edev;
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/*
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* If PHB supports compound PE, to fetch
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* the master PE because slave PE is invisible
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* to EEH core.
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*/
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pnv_pe = &phb->ioda.pe_array[pe_no];
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if (pnv_pe->flags & PNV_IODA_PE_SLAVE) {
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pnv_pe = pnv_pe->master;
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WARN_ON(!pnv_pe ||
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!(pnv_pe->flags & PNV_IODA_PE_MASTER));
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pe_no = pnv_pe->pe_number;
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}
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/* Find the PE according to PE# */
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memset(&edev, 0, sizeof(struct eeh_dev));
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edev.phb = hose;
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edev.pe_config_addr = pe_no;
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dev_pe = eeh_pe_get(&edev);
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if (!dev_pe)
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return -EEXIST;
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/* Freeze the (compound) PE */
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*pe = dev_pe;
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if (!(dev_pe->state & EEH_PE_ISOLATED))
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phb->freeze_pe(phb, pe_no);
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/*
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* At this point, we're sure the (compound) PE should
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* have been frozen. However, we still need poke until
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* hitting the frozen PE on top level.
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*/
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dev_pe = dev_pe->parent;
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while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) {
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int ret;
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int active_flags = (EEH_STATE_MMIO_ACTIVE |
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EEH_STATE_DMA_ACTIVE);
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ret = eeh_ops->get_state(dev_pe, NULL);
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if (ret <= 0 || (ret & active_flags) == active_flags) {
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dev_pe = dev_pe->parent;
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continue;
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}
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/* Frozen parent PE */
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*pe = dev_pe;
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if (!(dev_pe->state & EEH_PE_ISOLATED))
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phb->freeze_pe(phb, dev_pe->addr);
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/* Next one */
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dev_pe = dev_pe->parent;
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}
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return 0;
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}
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/**
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* ioda_eeh_next_error - Retrieve next error for EEH core to handle
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* @pe: The affected PE
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*
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* The function is expected to be called by EEH core while it gets
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* special EEH event (without binding PE). The function calls to
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* OPAL APIs for next error to handle. The informational error is
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* handled internally by platform. However, the dead IOC, dead PHB,
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* fenced PHB and frozen PE should be handled by EEH core eventually.
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*/
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static int ioda_eeh_next_error(struct eeh_pe **pe)
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{
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struct pci_controller *hose;
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struct pnv_phb *phb;
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struct eeh_pe *phb_pe, *parent_pe;
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__be64 frozen_pe_no;
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__be16 err_type, severity;
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int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
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long rc;
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int state, ret = EEH_NEXT_ERR_NONE;
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/*
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* While running here, it's safe to purge the event queue.
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* And we should keep the cached OPAL notifier event sychronized
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* between the kernel and firmware.
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*/
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eeh_remove_event(NULL, false);
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opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
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list_for_each_entry(hose, &hose_list, list_node) {
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/*
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* If the subordinate PCI buses of the PHB has been
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* removed or is exactly under error recovery, we
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* needn't take care of it any more.
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*/
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phb = hose->private_data;
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phb_pe = eeh_phb_pe_get(hose);
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if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
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continue;
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rc = opal_pci_next_error(phb->opal_id,
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&frozen_pe_no, &err_type, &severity);
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/* If OPAL API returns error, we needn't proceed */
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if (rc != OPAL_SUCCESS) {
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pr_devel("%s: Invalid return value on "
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"PHB#%x (0x%lx) from opal_pci_next_error",
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__func__, hose->global_number, rc);
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continue;
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}
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/* If the PHB doesn't have error, stop processing */
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if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR ||
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be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) {
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pr_devel("%s: No error found on PHB#%x\n",
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__func__, hose->global_number);
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continue;
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}
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/*
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* Processing the error. We're expecting the error with
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* highest priority reported upon multiple errors on the
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* specific PHB.
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*/
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pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
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__func__, be16_to_cpu(err_type), be16_to_cpu(severity),
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be64_to_cpu(frozen_pe_no), hose->global_number);
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switch (be16_to_cpu(err_type)) {
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case OPAL_EEH_IOC_ERROR:
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if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) {
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pr_err("EEH: dead IOC detected\n");
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ret = EEH_NEXT_ERR_DEAD_IOC;
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} else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
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pr_info("EEH: IOC informative error "
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"detected\n");
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ioda_eeh_hub_diag(hose);
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ret = EEH_NEXT_ERR_NONE;
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}
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break;
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case OPAL_EEH_PHB_ERROR:
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if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) {
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*pe = phb_pe;
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pr_err("EEH: dead PHB#%x detected, "
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"location: %s\n",
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hose->global_number,
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eeh_pe_loc_get(phb_pe));
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ret = EEH_NEXT_ERR_DEAD_PHB;
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} else if (be16_to_cpu(severity) ==
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OPAL_EEH_SEV_PHB_FENCED) {
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*pe = phb_pe;
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pr_err("EEH: Fenced PHB#%x detected, "
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"location: %s\n",
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hose->global_number,
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eeh_pe_loc_get(phb_pe));
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ret = EEH_NEXT_ERR_FENCED_PHB;
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} else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
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pr_info("EEH: PHB#%x informative error "
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"detected, location: %s\n",
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hose->global_number,
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eeh_pe_loc_get(phb_pe));
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ioda_eeh_phb_diag(phb_pe);
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pnv_pci_dump_phb_diag_data(hose, phb_pe->data);
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ret = EEH_NEXT_ERR_NONE;
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}
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break;
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case OPAL_EEH_PE_ERROR:
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/*
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* If we can't find the corresponding PE, we
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* just try to unfreeze.
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*/
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if (ioda_eeh_get_pe(hose,
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be64_to_cpu(frozen_pe_no), pe)) {
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/* Try best to clear it */
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pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n",
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hose->global_number, frozen_pe_no);
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pr_info("EEH: PHB location: %s\n",
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eeh_pe_loc_get(phb_pe));
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opal_pci_eeh_freeze_clear(phb->opal_id, frozen_pe_no,
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OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
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ret = EEH_NEXT_ERR_NONE;
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} else if ((*pe)->state & EEH_PE_ISOLATED ||
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eeh_pe_passed(*pe)) {
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ret = EEH_NEXT_ERR_NONE;
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} else {
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pr_err("EEH: Frozen PE#%x on PHB#%x detected\n",
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(*pe)->addr, (*pe)->phb->global_number);
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pr_err("EEH: PE location: %s, PHB location: %s\n",
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eeh_pe_loc_get(*pe), eeh_pe_loc_get(phb_pe));
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ret = EEH_NEXT_ERR_FROZEN_PE;
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}
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break;
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default:
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pr_warn("%s: Unexpected error type %d\n",
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__func__, be16_to_cpu(err_type));
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}
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/*
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* EEH core will try recover from fenced PHB or
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* frozen PE. In the time for frozen PE, EEH core
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* enable IO path for that before collecting logs,
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* but it ruins the site. So we have to dump the
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* log in advance here.
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*/
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if ((ret == EEH_NEXT_ERR_FROZEN_PE ||
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ret == EEH_NEXT_ERR_FENCED_PHB) &&
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!((*pe)->state & EEH_PE_ISOLATED)) {
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eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
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ioda_eeh_phb_diag(*pe);
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if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
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pnv_pci_dump_phb_diag_data((*pe)->phb,
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(*pe)->data);
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}
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/*
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* We probably have the frozen parent PE out there and
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* we need have to handle frozen parent PE firstly.
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*/
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if (ret == EEH_NEXT_ERR_FROZEN_PE) {
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parent_pe = (*pe)->parent;
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while (parent_pe) {
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/* Hit the ceiling ? */
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if (parent_pe->type & EEH_PE_PHB)
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break;
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/* Frozen parent PE ? */
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state = eeh_ops->get_state(parent_pe, NULL);
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if (state > 0 &&
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(state & active_flags) != active_flags)
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*pe = parent_pe;
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/* Next parent level */
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parent_pe = parent_pe->parent;
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}
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/* We possibly migrate to another PE */
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eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
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}
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/*
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* If we have no errors on the specific PHB or only
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* informative error there, we continue poking it.
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* Otherwise, we need actions to be taken by upper
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* layer.
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*/
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if (ret > EEH_NEXT_ERR_INF)
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break;
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}
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return ret;
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}
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struct pnv_eeh_ops ioda_eeh_ops = {
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.reset = ioda_eeh_reset,
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.next_error = ioda_eeh_next_error
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};
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@ -840,26 +840,346 @@ static int pnv_eeh_write_config(struct device_node *dn,
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return pnv_pci_cfg_write(dn, where, size, val);
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}
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static void pnv_eeh_dump_hub_diag_common(struct OpalIoP7IOCErrorData *data)
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{
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/* GEM */
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if (data->gemXfir || data->gemRfir ||
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data->gemRirqfir || data->gemMask || data->gemRwof)
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pr_info(" GEM: %016llx %016llx %016llx %016llx %016llx\n",
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be64_to_cpu(data->gemXfir),
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be64_to_cpu(data->gemRfir),
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be64_to_cpu(data->gemRirqfir),
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be64_to_cpu(data->gemMask),
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be64_to_cpu(data->gemRwof));
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/* LEM */
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if (data->lemFir || data->lemErrMask ||
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data->lemAction0 || data->lemAction1 || data->lemWof)
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pr_info(" LEM: %016llx %016llx %016llx %016llx %016llx\n",
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be64_to_cpu(data->lemFir),
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be64_to_cpu(data->lemErrMask),
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be64_to_cpu(data->lemAction0),
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be64_to_cpu(data->lemAction1),
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be64_to_cpu(data->lemWof));
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}
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static void pnv_eeh_get_and_dump_hub_diag(struct pci_controller *hose)
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{
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struct pnv_phb *phb = hose->private_data;
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struct OpalIoP7IOCErrorData *data = &phb->diag.hub_diag;
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long rc;
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rc = opal_pci_get_hub_diag_data(phb->hub_id, data, sizeof(*data));
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if (rc != OPAL_SUCCESS) {
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pr_warn("%s: Failed to get HUB#%llx diag-data (%ld)\n",
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__func__, phb->hub_id, rc);
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return;
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}
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switch (data->type) {
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case OPAL_P7IOC_DIAG_TYPE_RGC:
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pr_info("P7IOC diag-data for RGC\n\n");
|
||||
pnv_eeh_dump_hub_diag_common(data);
|
||||
if (data->rgc.rgcStatus || data->rgc.rgcLdcp)
|
||||
pr_info(" RGC: %016llx %016llx\n",
|
||||
be64_to_cpu(data->rgc.rgcStatus),
|
||||
be64_to_cpu(data->rgc.rgcLdcp));
|
||||
break;
|
||||
case OPAL_P7IOC_DIAG_TYPE_BI:
|
||||
pr_info("P7IOC diag-data for BI %s\n\n",
|
||||
data->bi.biDownbound ? "Downbound" : "Upbound");
|
||||
pnv_eeh_dump_hub_diag_common(data);
|
||||
if (data->bi.biLdcp0 || data->bi.biLdcp1 ||
|
||||
data->bi.biLdcp2 || data->bi.biFenceStatus)
|
||||
pr_info(" BI: %016llx %016llx %016llx %016llx\n",
|
||||
be64_to_cpu(data->bi.biLdcp0),
|
||||
be64_to_cpu(data->bi.biLdcp1),
|
||||
be64_to_cpu(data->bi.biLdcp2),
|
||||
be64_to_cpu(data->bi.biFenceStatus));
|
||||
break;
|
||||
case OPAL_P7IOC_DIAG_TYPE_CI:
|
||||
pr_info("P7IOC diag-data for CI Port %d\n\n",
|
||||
data->ci.ciPort);
|
||||
pnv_eeh_dump_hub_diag_common(data);
|
||||
if (data->ci.ciPortStatus || data->ci.ciPortLdcp)
|
||||
pr_info(" CI: %016llx %016llx\n",
|
||||
be64_to_cpu(data->ci.ciPortStatus),
|
||||
be64_to_cpu(data->ci.ciPortLdcp));
|
||||
break;
|
||||
case OPAL_P7IOC_DIAG_TYPE_MISC:
|
||||
pr_info("P7IOC diag-data for MISC\n\n");
|
||||
pnv_eeh_dump_hub_diag_common(data);
|
||||
break;
|
||||
case OPAL_P7IOC_DIAG_TYPE_I2C:
|
||||
pr_info("P7IOC diag-data for I2C\n\n");
|
||||
pnv_eeh_dump_hub_diag_common(data);
|
||||
break;
|
||||
default:
|
||||
pr_warn("%s: Invalid type of HUB#%llx diag-data (%d)\n",
|
||||
__func__, phb->hub_id, data->type);
|
||||
}
|
||||
}
|
||||
|
||||
static int pnv_eeh_get_pe(struct pci_controller *hose,
|
||||
u16 pe_no, struct eeh_pe **pe)
|
||||
{
|
||||
struct pnv_phb *phb = hose->private_data;
|
||||
struct pnv_ioda_pe *pnv_pe;
|
||||
struct eeh_pe *dev_pe;
|
||||
struct eeh_dev edev;
|
||||
|
||||
/*
|
||||
* If PHB supports compound PE, to fetch
|
||||
* the master PE because slave PE is invisible
|
||||
* to EEH core.
|
||||
*/
|
||||
pnv_pe = &phb->ioda.pe_array[pe_no];
|
||||
if (pnv_pe->flags & PNV_IODA_PE_SLAVE) {
|
||||
pnv_pe = pnv_pe->master;
|
||||
WARN_ON(!pnv_pe ||
|
||||
!(pnv_pe->flags & PNV_IODA_PE_MASTER));
|
||||
pe_no = pnv_pe->pe_number;
|
||||
}
|
||||
|
||||
/* Find the PE according to PE# */
|
||||
memset(&edev, 0, sizeof(struct eeh_dev));
|
||||
edev.phb = hose;
|
||||
edev.pe_config_addr = pe_no;
|
||||
dev_pe = eeh_pe_get(&edev);
|
||||
if (!dev_pe)
|
||||
return -EEXIST;
|
||||
|
||||
/* Freeze the (compound) PE */
|
||||
*pe = dev_pe;
|
||||
if (!(dev_pe->state & EEH_PE_ISOLATED))
|
||||
phb->freeze_pe(phb, pe_no);
|
||||
|
||||
/*
|
||||
* At this point, we're sure the (compound) PE should
|
||||
* have been frozen. However, we still need poke until
|
||||
* hitting the frozen PE on top level.
|
||||
*/
|
||||
dev_pe = dev_pe->parent;
|
||||
while (dev_pe && !(dev_pe->type & EEH_PE_PHB)) {
|
||||
int ret;
|
||||
int active_flags = (EEH_STATE_MMIO_ACTIVE |
|
||||
EEH_STATE_DMA_ACTIVE);
|
||||
|
||||
ret = eeh_ops->get_state(dev_pe, NULL);
|
||||
if (ret <= 0 || (ret & active_flags) == active_flags) {
|
||||
dev_pe = dev_pe->parent;
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Frozen parent PE */
|
||||
*pe = dev_pe;
|
||||
if (!(dev_pe->state & EEH_PE_ISOLATED))
|
||||
phb->freeze_pe(phb, dev_pe->addr);
|
||||
|
||||
/* Next one */
|
||||
dev_pe = dev_pe->parent;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* pnv_eeh_next_error - Retrieve next EEH error to handle
|
||||
* @pe: Affected PE
|
||||
*
|
||||
* Using OPAL API, to retrieve next EEH error for EEH core to handle
|
||||
* The function is expected to be called by EEH core while it gets
|
||||
* special EEH event (without binding PE). The function calls to
|
||||
* OPAL APIs for next error to handle. The informational error is
|
||||
* handled internally by platform. However, the dead IOC, dead PHB,
|
||||
* fenced PHB and frozen PE should be handled by EEH core eventually.
|
||||
*/
|
||||
static int pnv_eeh_next_error(struct eeh_pe **pe)
|
||||
{
|
||||
struct pci_controller *hose;
|
||||
struct pnv_phb *phb = NULL;
|
||||
struct pnv_phb *phb;
|
||||
struct eeh_pe *phb_pe, *parent_pe;
|
||||
__be64 frozen_pe_no;
|
||||
__be16 err_type, severity;
|
||||
int active_flags = (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
|
||||
long rc;
|
||||
int state, ret = EEH_NEXT_ERR_NONE;
|
||||
|
||||
/*
|
||||
* While running here, it's safe to purge the event queue.
|
||||
* And we should keep the cached OPAL notifier event sychronized
|
||||
* between the kernel and firmware.
|
||||
*/
|
||||
eeh_remove_event(NULL, false);
|
||||
opal_notifier_update_evt(OPAL_EVENT_PCI_ERROR, 0x0ul);
|
||||
|
||||
list_for_each_entry(hose, &hose_list, list_node) {
|
||||
/*
|
||||
* If the subordinate PCI buses of the PHB has been
|
||||
* removed or is exactly under error recovery, we
|
||||
* needn't take care of it any more.
|
||||
*/
|
||||
phb = hose->private_data;
|
||||
break;
|
||||
phb_pe = eeh_phb_pe_get(hose);
|
||||
if (!phb_pe || (phb_pe->state & EEH_PE_ISOLATED))
|
||||
continue;
|
||||
|
||||
rc = opal_pci_next_error(phb->opal_id,
|
||||
&frozen_pe_no, &err_type, &severity);
|
||||
if (rc != OPAL_SUCCESS) {
|
||||
pr_devel("%s: Invalid return value on "
|
||||
"PHB#%x (0x%lx) from opal_pci_next_error",
|
||||
__func__, hose->global_number, rc);
|
||||
continue;
|
||||
}
|
||||
|
||||
/* If the PHB doesn't have error, stop processing */
|
||||
if (be16_to_cpu(err_type) == OPAL_EEH_NO_ERROR ||
|
||||
be16_to_cpu(severity) == OPAL_EEH_SEV_NO_ERROR) {
|
||||
pr_devel("%s: No error found on PHB#%x\n",
|
||||
__func__, hose->global_number);
|
||||
continue;
|
||||
}
|
||||
|
||||
/*
|
||||
* Processing the error. We're expecting the error with
|
||||
* highest priority reported upon multiple errors on the
|
||||
* specific PHB.
|
||||
*/
|
||||
pr_devel("%s: Error (%d, %d, %llu) on PHB#%x\n",
|
||||
__func__, be16_to_cpu(err_type),
|
||||
be16_to_cpu(severity), be64_to_cpu(frozen_pe_no),
|
||||
hose->global_number);
|
||||
switch (be16_to_cpu(err_type)) {
|
||||
case OPAL_EEH_IOC_ERROR:
|
||||
if (be16_to_cpu(severity) == OPAL_EEH_SEV_IOC_DEAD) {
|
||||
pr_err("EEH: dead IOC detected\n");
|
||||
ret = EEH_NEXT_ERR_DEAD_IOC;
|
||||
} else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
|
||||
pr_info("EEH: IOC informative error "
|
||||
"detected\n");
|
||||
pnv_eeh_get_and_dump_hub_diag(hose);
|
||||
ret = EEH_NEXT_ERR_NONE;
|
||||
}
|
||||
|
||||
break;
|
||||
case OPAL_EEH_PHB_ERROR:
|
||||
if (be16_to_cpu(severity) == OPAL_EEH_SEV_PHB_DEAD) {
|
||||
*pe = phb_pe;
|
||||
pr_err("EEH: dead PHB#%x detected, "
|
||||
"location: %s\n",
|
||||
hose->global_number,
|
||||
eeh_pe_loc_get(phb_pe));
|
||||
ret = EEH_NEXT_ERR_DEAD_PHB;
|
||||
} else if (be16_to_cpu(severity) ==
|
||||
OPAL_EEH_SEV_PHB_FENCED) {
|
||||
*pe = phb_pe;
|
||||
pr_err("EEH: Fenced PHB#%x detected, "
|
||||
"location: %s\n",
|
||||
hose->global_number,
|
||||
eeh_pe_loc_get(phb_pe));
|
||||
ret = EEH_NEXT_ERR_FENCED_PHB;
|
||||
} else if (be16_to_cpu(severity) == OPAL_EEH_SEV_INF) {
|
||||
pr_info("EEH: PHB#%x informative error "
|
||||
"detected, location: %s\n",
|
||||
hose->global_number,
|
||||
eeh_pe_loc_get(phb_pe));
|
||||
pnv_eeh_get_phb_diag(phb_pe);
|
||||
pnv_pci_dump_phb_diag_data(hose, phb_pe->data);
|
||||
ret = EEH_NEXT_ERR_NONE;
|
||||
}
|
||||
|
||||
break;
|
||||
case OPAL_EEH_PE_ERROR:
|
||||
/*
|
||||
* If we can't find the corresponding PE, we
|
||||
* just try to unfreeze.
|
||||
*/
|
||||
if (pnv_eeh_get_pe(hose,
|
||||
be64_to_cpu(frozen_pe_no), pe)) {
|
||||
/* Try best to clear it */
|
||||
pr_info("EEH: Clear non-existing PHB#%x-PE#%llx\n",
|
||||
hose->global_number, frozen_pe_no);
|
||||
pr_info("EEH: PHB location: %s\n",
|
||||
eeh_pe_loc_get(phb_pe));
|
||||
opal_pci_eeh_freeze_clear(phb->opal_id,
|
||||
frozen_pe_no,
|
||||
OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
|
||||
ret = EEH_NEXT_ERR_NONE;
|
||||
} else if ((*pe)->state & EEH_PE_ISOLATED ||
|
||||
eeh_pe_passed(*pe)) {
|
||||
ret = EEH_NEXT_ERR_NONE;
|
||||
} else {
|
||||
pr_err("EEH: Frozen PE#%x "
|
||||
"on PHB#%x detected\n",
|
||||
(*pe)->addr,
|
||||
(*pe)->phb->global_number);
|
||||
pr_err("EEH: PE location: %s, "
|
||||
"PHB location: %s\n",
|
||||
eeh_pe_loc_get(*pe),
|
||||
eeh_pe_loc_get(phb_pe));
|
||||
ret = EEH_NEXT_ERR_FROZEN_PE;
|
||||
}
|
||||
|
||||
break;
|
||||
default:
|
||||
pr_warn("%s: Unexpected error type %d\n",
|
||||
__func__, be16_to_cpu(err_type));
|
||||
}
|
||||
|
||||
/*
|
||||
* EEH core will try recover from fenced PHB or
|
||||
* frozen PE. In the time for frozen PE, EEH core
|
||||
* enable IO path for that before collecting logs,
|
||||
* but it ruins the site. So we have to dump the
|
||||
* log in advance here.
|
||||
*/
|
||||
if ((ret == EEH_NEXT_ERR_FROZEN_PE ||
|
||||
ret == EEH_NEXT_ERR_FENCED_PHB) &&
|
||||
!((*pe)->state & EEH_PE_ISOLATED)) {
|
||||
eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
|
||||
pnv_eeh_get_phb_diag(*pe);
|
||||
|
||||
if (eeh_has_flag(EEH_EARLY_DUMP_LOG))
|
||||
pnv_pci_dump_phb_diag_data((*pe)->phb,
|
||||
(*pe)->data);
|
||||
}
|
||||
|
||||
/*
|
||||
* We probably have the frozen parent PE out there and
|
||||
* we need have to handle frozen parent PE firstly.
|
||||
*/
|
||||
if (ret == EEH_NEXT_ERR_FROZEN_PE) {
|
||||
parent_pe = (*pe)->parent;
|
||||
while (parent_pe) {
|
||||
/* Hit the ceiling ? */
|
||||
if (parent_pe->type & EEH_PE_PHB)
|
||||
break;
|
||||
|
||||
/* Frozen parent PE ? */
|
||||
state = eeh_ops->get_state(parent_pe, NULL);
|
||||
if (state > 0 &&
|
||||
(state & active_flags) != active_flags)
|
||||
*pe = parent_pe;
|
||||
|
||||
/* Next parent level */
|
||||
parent_pe = parent_pe->parent;
|
||||
}
|
||||
|
||||
/* We possibly migrate to another PE */
|
||||
eeh_pe_state_mark(*pe, EEH_PE_ISOLATED);
|
||||
}
|
||||
|
||||
/*
|
||||
* If we have no errors on the specific PHB or only
|
||||
* informative error there, we continue poking it.
|
||||
* Otherwise, we need actions to be taken by upper
|
||||
* layer.
|
||||
*/
|
||||
if (ret > EEH_NEXT_ERR_INF)
|
||||
break;
|
||||
}
|
||||
|
||||
if (phb && phb->eeh_ops->next_error)
|
||||
return phb->eeh_ops->next_error(pe);
|
||||
|
||||
return -EEXIST;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int pnv_eeh_restore_config(struct device_node *dn)
|
||||
|
||||
@ -79,7 +79,6 @@ struct pnv_ioda_pe {
|
||||
#ifdef CONFIG_EEH
|
||||
struct pnv_eeh_ops {
|
||||
int (*reset)(struct eeh_pe *pe, int option);
|
||||
int (*next_error)(struct eeh_pe **pe);
|
||||
};
|
||||
#endif /* CONFIG_EEH */
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user