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clk: rockchip: fix clock select order for rk3288 usbphy480m_src

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According to rk3288 trm, the mux selector locate at bit[12:11]
of CRU_CLKSEL13_CON shows:
2'b00: select HOST0 USB pll clock (clk_otgphy1)
2'b01: select HOST1 USB pll clock (clk_otgphy2)
2'b10: select OTG USB pll clock   (clk_otgphy0)

The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3
- clk_otgphy0 -> USB PHY OTG
- clk_otgphy1 -> USB PHY host0
- clk_otgphy2 -> USB PHY host1

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
This commit is contained in:
Kever Yang 2014-11-13 16:11:49 +08:00 committed by Heiko Stuebner
parent 0132234160
commit 29e9446851
1 changed files with 2 additions and 2 deletions
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4
drivers/clk/rockchip/clk-rk3288.c
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@ -195,8 +195,8 @@ PNAME(mux_hsadcout_p) = { "hsadc_src", "ext_hsadc" };
PNAME(mux_edp_24m_p) = { "ext_edp_24m", "xin24m" };
PNAME(mux_tspout_p) = { "cpll", "gpll", "npll", "xin27m" };
PNAME(mux_usbphy480m_p) = { "sclk_otgphy0", "sclk_otgphy1",
"sclk_otgphy2" };
PNAME(mux_usbphy480m_p) = { "sclk_otgphy1", "sclk_otgphy2",
"sclk_otgphy0" };
PNAME(mux_hsicphy480m_p) = { "cpll", "gpll", "usbphy480m_src" };
PNAME(mux_hsicphy12m_p) = { "hsicphy12m_xin12m", "hsicphy12m_usbphy" };