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ARM: mvebu: Conform L2CC node with ePAPR specification by adding cache-level

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For L2 cache controller node, cache-level property is mandatory. Let's
add it to Armada 370 and Armada XP device tree.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
This commit is contained in:
Gregory CLEMENT 2015-03-17 17:33:54 +01:00
parent b7f01842bc
commit 292a3546b9
2 changed files with 2 additions and 0 deletions
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1
arch/arm/boot/dts/armada-370.dtsi
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@ -129,6 +129,7 @@ L2: l2-cache {
compatible = "marvell,aurora-outer-cache"; compatible = "marvell,aurora-outer-cache";
reg = <0x08000 0x1000>; reg = <0x08000 0x1000>;
cache-id-part = <0x100>; cache-id-part = <0x100>;
cache-level = <2>;
cache-unified; cache-unified;
wt-override; wt-override;
}; };

1
arch/arm/boot/dts/armada-xp.dtsi
View File

@ -79,6 +79,7 @@ L2: l2-cache {
compatible = "marvell,aurora-system-cache"; compatible = "marvell,aurora-system-cache";
reg = <0x08000 0x1000>; reg = <0x08000 0x1000>;
cache-id-part = <0x100>; cache-id-part = <0x100>;
cache-level = <2>;
cache-unified; cache-unified;
wt-override; wt-override;
}; };