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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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sh: intc - add support for SH7710
This patch converts the cpu specific interrupt setup code for sh7710 from ipr to intc. While at it new vectors are added to match the information provided by the datasheet. Version two simplifies the Kconfig part. Vectors for IRQ4 and IRQ5 are enabled by default. Use plat_irq_setup_pins() if pins IRQ0-3 should be used in IRQ mode. This patch also adds sh7710 specific platform data for the rtc driver. The base address of SCIF1 is adjusted to match the datasheet. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Magnus Damm
Paul Mundt
parent
70e8be0a4e
commit
28b146c84e
@ -10,9 +10,128 @@
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*/
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/serial.h>
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#include <asm/sci.h>
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enum {
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UNUSED = 0,
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/* interrupt sources */
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IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
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DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3,
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SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI,
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SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI,
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DMAC_DEI4, DMAC_DEI5,
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IPSEC,
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EDMAC0, EDMAC1, EDMAC2,
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SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI,
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SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI,
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TMU0, TMU1, TMU2,
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RTC_ATI, RTC_PRI, RTC_CUI,
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WDT,
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REF,
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/* interrupt groups */
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RTC, DMAC1, SCIF0, SCIF1, DMAC2, SIOF0, SIOF1,
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};
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static struct intc_vect vectors[] = {
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INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
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INTC_VECT(DMAC_DEI0, 0x800), INTC_VECT(DMAC_DEI1, 0x820),
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INTC_VECT(DMAC_DEI2, 0x840), INTC_VECT(DMAC_DEI3, 0x860),
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INTC_VECT(SCIF0_ERI, 0x880), INTC_VECT(SCIF0_RXI, 0x8a0),
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INTC_VECT(SCIF0_BRI, 0x8c0), INTC_VECT(SCIF0_TXI, 0x8e0),
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INTC_VECT(SCIF1_ERI, 0x900), INTC_VECT(SCIF1_RXI, 0x920),
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INTC_VECT(SCIF1_BRI, 0x940), INTC_VECT(SCIF1_TXI, 0x960),
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INTC_VECT(DMAC_DEI4, 0xb80), INTC_VECT(DMAC_DEI5, 0xba0),
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INTC_VECT(IPSEC, 0xbe0),
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INTC_VECT(EDMAC0, 0xc00), INTC_VECT(EDMAC1, 0xc20),
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INTC_VECT(EDMAC2, 0xc40),
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INTC_VECT(SIOF0_ERI, 0xe00), INTC_VECT(SIOF0_TXI, 0xe20),
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INTC_VECT(SIOF0_RXI, 0xe40), INTC_VECT(SIOF0_CCI, 0xe60),
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INTC_VECT(SIOF1_ERI, 0xe80), INTC_VECT(SIOF1_TXI, 0xea0),
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INTC_VECT(SIOF1_RXI, 0xec0), INTC_VECT(SIOF1_CCI, 0xee0),
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INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
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INTC_VECT(TMU2, 0x440),
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INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
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INTC_VECT(RTC_CUI, 0x4c0),
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INTC_VECT(WDT, 0x560),
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INTC_VECT(REF, 0x580),
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};
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static struct intc_group groups[] = {
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INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
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INTC_GROUP(DMAC1, DMAC_DEI0, DMAC_DEI1, DMAC_DEI2, DMAC_DEI3),
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INTC_GROUP(SCIF0, SCIF0_ERI, SCIF0_RXI, SCIF0_BRI, SCIF0_TXI),
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INTC_GROUP(SCIF1, SCIF1_ERI, SCIF1_RXI, SCIF1_BRI, SCIF1_TXI),
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INTC_GROUP(DMAC2, DMAC_DEI4, DMAC_DEI5),
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INTC_GROUP(SIOF0, SIOF0_ERI, SIOF0_TXI, SIOF0_RXI, SIOF0_CCI),
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INTC_GROUP(SIOF1, SIOF1_ERI, SIOF1_TXI, SIOF1_RXI, SIOF1_CCI),
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};
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static struct intc_prio priorities[] = {
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INTC_PRIO(DMAC1, 7),
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INTC_PRIO(DMAC2, 7),
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INTC_PRIO(SCIF0, 3),
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INTC_PRIO(SCIF1, 3),
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INTC_PRIO(SIOF0, 3),
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INTC_PRIO(SIOF1, 3),
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INTC_PRIO(EDMAC0, 5),
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INTC_PRIO(EDMAC1, 5),
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INTC_PRIO(EDMAC2, 5),
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};
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static struct intc_prio_reg prio_registers[] = {
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{ 0xfffffee2, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2, RTC } },
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{ 0xfffffee4, 16, 4, /* IPRB */ { WDT, REF, 0, 0 } },
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{ 0xa4000016, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
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{ 0xa4000018, 16, 4, /* IPRD */ { 0, 0, IRQ4, IRQ5 } },
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{ 0xa400001a, 16, 4, /* IPRE */ { DMAC1, SCIF0, SCIF1 } },
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{ 0xa4080000, 16, 4, /* IPRF */ { IPSEC, DMAC2 } },
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{ 0xa4080002, 16, 4, /* IPRG */ { EDMAC0, EDMAC1, EDMAC2 } },
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{ 0xa4080004, 16, 4, /* IPRH */ { 0, 0, 0, SIOF0 } },
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{ 0xa4080006, 16, 4, /* IPRI */ { 0, 0, SIOF1 } },
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};
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static DECLARE_INTC_DESC(intc_desc, "sh7710", vectors, groups,
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priorities, NULL, prio_registers, NULL);
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static struct intc_vect vectors_irq[] = {
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INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
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INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
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};
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static DECLARE_INTC_DESC(intc_desc_irq, "sh7710-irq", vectors_irq, NULL,
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priorities, NULL, prio_registers, NULL);
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static struct resource rtc_resources[] = {
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[0] = {
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.start = 0xa413fec0,
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.end = 0xa413fec0 + 0x1e,
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.flags = IORESOURCE_IO,
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},
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[1] = {
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.start = 20,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = 21,
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.flags = IORESOURCE_IRQ,
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},
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[3] = {
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.start = 22,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device rtc_device = {
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.name = "sh-rtc",
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.id = -1,
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.num_resources = ARRAY_SIZE(rtc_resources),
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.resource = rtc_resources,
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};
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static struct plat_sci_port sci_platform_data[] = {
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{
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.mapbase = 0xa4400000,
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@ -20,7 +139,7 @@ static struct plat_sci_port sci_platform_data[] = {
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.type = PORT_SCIF,
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.irqs = { 52, 53, 55, 54 },
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}, {
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.mapbase = 0xa4420000,
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.mapbase = 0xa4410000,
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.flags = UPF_BOOT_AUTOCONF,
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.type = PORT_SCIF,
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.irqs = { 56, 57, 59, 58 },
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@ -40,6 +159,7 @@ static struct platform_device sci_device = {
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static struct platform_device *sh7710_devices[] __initdata = {
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&sci_device,
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&rtc_device,
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};
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static int __init sh7710_devices_setup(void)
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@ -49,59 +169,16 @@ static int __init sh7710_devices_setup(void)
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}
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__initcall(sh7710_devices_setup);
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static struct ipr_data ipr_irq_table[] = {
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/* IRQ, IPR-idx, shift, priority */
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{ 16, 0, 12, 2 }, /* TMU0 TUNI*/
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{ 17, 0, 8, 2 }, /* TMU1 TUNI */
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{ 18, 0, 4, 2 }, /* TMU2 TUNI */
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{ 27, 1, 12, 2 }, /* WDT ITI */
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{ 20, 0, 0, 2 }, /* RTC ATI (alarm) */
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{ 21, 0, 0, 2 }, /* RTC PRI (period) */
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{ 22, 0, 0, 2 }, /* RTC CUI (carry) */
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{ 48, 4, 12, 7 }, /* DMAC DMTE0 */
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{ 49, 4, 12, 7 }, /* DMAC DMTE1 */
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{ 50, 4, 12, 7 }, /* DMAC DMTE2 */
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{ 51, 4, 12, 7 }, /* DMAC DMTE3 */
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{ 52, 4, 8, 3 }, /* SCIF0 ERI */
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{ 53, 4, 8, 3 }, /* SCIF0 RXI */
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{ 54, 4, 8, 3 }, /* SCIF0 BRI */
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{ 55, 4, 8, 3 }, /* SCIF0 TXI */
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{ 56, 4, 4, 3 }, /* SCIF1 ERI */
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{ 57, 4, 4, 3 }, /* SCIF1 RXI */
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{ 58, 4, 4, 3 }, /* SCIF1 BRI */
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{ 59, 4, 4, 3 }, /* SCIF1 TXI */
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{ 76, 5, 8, 7 }, /* DMAC DMTE4 */
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{ 77, 5, 8, 7 }, /* DMAC DMTE5 */
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{ 80, 6, 12, 5 }, /* EDMAC EINT0 */
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{ 81, 6, 8, 5 }, /* EDMAC EINT1 */
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{ 82, 6, 4, 5 }, /* EDMAC EINT2 */
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};
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static unsigned long ipr_offsets[] = {
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0xA414FEE2, /* 0: IPRA */
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0xA414FEE4, /* 1: IPRB */
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0xA4140016, /* 2: IPRC */
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0xA4140018, /* 3: IPRD */
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0xA414001A, /* 4: IPRE */
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0xA4080000, /* 5: IPRF */
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0xA4080002, /* 6: IPRG */
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0xA4080004, /* 7: IPRH */
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0xA4080006, /* 8: IPRI */
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};
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static struct ipr_desc ipr_irq_desc = {
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.ipr_offsets = ipr_offsets,
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.nr_offsets = ARRAY_SIZE(ipr_offsets),
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.ipr_data = ipr_irq_table,
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.nr_irqs = ARRAY_SIZE(ipr_irq_table),
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.chip = {
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.name = "IPR-sh7710",
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},
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};
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void __init plat_irq_setup_pins(int mode)
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{
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if (mode == IRQ_MODE_IRQ) {
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register_intc_controller(&intc_desc_irq);
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return;
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}
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BUG();
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}
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void __init plat_irq_setup(void)
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{
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register_ipr_controller(&ipr_irq_desc);
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register_intc_controller(&intc_desc);
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}
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@ -98,7 +98,7 @@ config CPU_SUBTYPE_SH7709
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config CPU_SUBTYPE_SH7710
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bool "Support SH7710 processor"
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select CPU_SH3
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select CPU_HAS_IPR_IRQ
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select CPU_HAS_INTC_IRQ
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select CPU_HAS_DSP
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help
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Select SH7710 if you have a SH3-DSP SH7710 CPU.
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@ -106,7 +106,7 @@ config CPU_SUBTYPE_SH7710
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config CPU_SUBTYPE_SH7712
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bool "Support SH7712 processor"
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select CPU_SH3
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select CPU_HAS_IPR_IRQ
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select CPU_HAS_INTC_IRQ
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select CPU_HAS_DSP
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help
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Select SH7712 if you have a SH3-DSP SH7712 CPU.
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