mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 00:20:15 +07:00
drm/i915: Convert cdclk to global state
Let's convert cdclk_state to be a proper global state. That allows us to use the regular atomic old vs. new state accessor, hopefully making the code less confusing. We do have to deal with a few more error cases in case the cdclk state duplication fails. But so be it. v2: Fix new plane min_cdclk vs. old crtc min_cdclk check Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200121140353.25997-1-ville.syrjala@linux.intel.com Reviewed-by: Imre Deak <imre.deak@intel.com>
This commit is contained in:
Ville Syrjälä
parent
aac978718b
commit
28a30b45f5
@ -520,7 +520,6 @@ void intel_atomic_state_clear(struct drm_atomic_state *s)
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state->dpll_set = state->modeset = false;
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state->global_state_changed = false;
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state->active_pipes = 0;
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intel_cdclk_clear_state(state);
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}
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struct intel_crtc_state *
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@ -37,6 +37,7 @@
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#include "i915_trace.h"
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#include "intel_atomic_plane.h"
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#include "intel_cdclk.h"
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#include "intel_display_types.h"
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#include "intel_pm.h"
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#include "intel_sprite.h"
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@ -155,45 +156,63 @@ unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
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return cpp * crtc_state->pixel_rate;
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}
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bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
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struct intel_plane *plane)
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int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
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struct intel_plane *plane,
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bool *need_cdclk_calc)
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{
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struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
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const struct intel_cdclk_state *cdclk_state =
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&dev_priv->cdclk_state;
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const struct intel_plane_state *plane_state =
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intel_atomic_get_new_plane_state(state, plane);
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struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
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struct intel_crtc_state *crtc_state;
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const struct intel_cdclk_state *cdclk_state;
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struct intel_crtc_state *new_crtc_state =
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intel_atomic_get_new_crtc_state(state, crtc);
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const struct intel_crtc_state *old_crtc_state =
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intel_atomic_get_old_crtc_state(state, crtc);
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if (!plane_state->uapi.visible || !plane->min_cdclk)
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return false;
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return 0;
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crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
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crtc_state->min_cdclk[plane->id] =
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plane->min_cdclk(crtc_state, plane_state);
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new_crtc_state->min_cdclk[plane->id] =
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plane->min_cdclk(new_crtc_state, plane_state);
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/*
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* Does the cdclk need to be bumbed up?
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* No need to check against the cdclk state if
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* the min cdclk for the plane doesn't increase.
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*
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* Note: we obviously need to be called before the new
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* cdclk frequency is calculated so state->cdclk.logical
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* hasn't been populated yet. Hence we look at the old
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* cdclk state under dev_priv->cdclk.logical. This is
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* safe as long we hold at least one crtc mutex (which
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* must be true since we have crtc_state).
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* Ie. we only ever increase the cdclk due to plane
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* requirements. This can reduce back and forth
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* display blinking due to constant cdclk changes.
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*/
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if (crtc_state->min_cdclk[plane->id] > cdclk_state->logical.cdclk) {
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drm_dbg_kms(&dev_priv->drm,
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"[PLANE:%d:%s] min_cdclk (%d kHz) > logical cdclk (%d kHz)\n",
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plane->base.base.id, plane->base.name,
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crtc_state->min_cdclk[plane->id],
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cdclk_state->logical.cdclk);
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return true;
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}
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if (new_crtc_state->min_cdclk[plane->id] <=
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old_crtc_state->min_cdclk[plane->id])
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return 0;
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return false;
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cdclk_state = intel_atomic_get_cdclk_state(state);
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if (IS_ERR(cdclk_state))
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return PTR_ERR(cdclk_state);
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/*
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* No need to recalculate the cdclk state if
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* the min cdclk for the pipe doesn't increase.
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*
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* Ie. we only ever increase the cdclk due to plane
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* requirements. This can reduce back and forth
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* display blinking due to constant cdclk changes.
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*/
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if (new_crtc_state->min_cdclk[plane->id] <=
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cdclk_state->min_cdclk[crtc->pipe])
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return 0;
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drm_dbg_kms(&dev_priv->drm,
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"[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
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plane->base.base.id, plane->base.name,
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new_crtc_state->min_cdclk[plane->id],
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crtc->base.base.id, crtc->base.name,
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cdclk_state->min_cdclk[crtc->pipe]);
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*need_cdclk_calc = true;
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return 0;
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}
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static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
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@ -46,7 +46,8 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
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struct intel_crtc_state *crtc_state,
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const struct intel_plane_state *old_plane_state,
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struct intel_plane_state *plane_state);
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bool intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
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struct intel_plane *plane);
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int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
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struct intel_plane *plane,
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bool *need_cdclk_calc);
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#endif /* __INTEL_ATOMIC_PLANE_H__ */
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@ -30,6 +30,7 @@
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#include "i915_drv.h"
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#include "intel_atomic.h"
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#include "intel_audio.h"
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#include "intel_cdclk.h"
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#include "intel_display_types.h"
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#include "intel_lpe_audio.h"
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@ -809,6 +810,34 @@ void intel_init_audio_hooks(struct drm_i915_private *dev_priv)
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}
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}
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static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
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bool enable)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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struct intel_cdclk_state *cdclk_state;
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struct intel_crtc *crtc;
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int ret;
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/* need to hold at least one crtc lock for the global state */
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crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
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ret = drm_modeset_lock(&crtc->base.mutex, state->base.acquire_ctx);
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if (ret)
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return ret;
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cdclk_state = intel_atomic_get_cdclk_state(state);
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if (IS_ERR(cdclk_state))
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return PTR_ERR(cdclk_state);
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cdclk_state->force_min_cdclk_changed = true;
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cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
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ret = intel_atomic_lock_global_state(&cdclk_state->base);
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if (ret)
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return ret;
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return drm_atomic_commit(&state->base);
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}
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static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
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bool enable)
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{
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@ -824,15 +853,7 @@ static void glk_force_audio_cdclk(struct drm_i915_private *dev_priv,
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state->acquire_ctx = &ctx;
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retry:
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to_intel_atomic_state(state)->cdclk_state.force_min_cdclk_changed = true;
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to_intel_atomic_state(state)->cdclk_state.force_min_cdclk =
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enable ? 2 * 96000 : 0;
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/* Protects dev_priv->cdclk.force_min_cdclk */
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ret = _intel_atomic_lock_global_state(to_intel_atomic_state(state));
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if (!ret)
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ret = drm_atomic_commit(state);
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ret = glk_force_audio_cdclk_commit(to_intel_atomic_state(state), enable);
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if (ret == -EDEADLK) {
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drm_atomic_state_clear(state);
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drm_modeset_backoff(&ctx);
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@ -1823,37 +1823,6 @@ static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
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a->voltage_level != b->voltage_level;
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}
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/**
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* intel_cdclk_clear_state - clear the cdclk state
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* @state: atomic state
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*
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* Clear the cdclk state for ww_mutex backoff.
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*/
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void intel_cdclk_clear_state(struct intel_atomic_state *state)
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{
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memset(&state->cdclk_state, 0, sizeof(state->cdclk_state));
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state->cdclk_state.pipe = INVALID_PIPE;
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}
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/**
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* intel_cdclk_swap_state - make atomic CDCLK configuration effective
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* @state: atomic state
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*
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* This is the CDCLK version of drm_atomic_helper_swap_state() since the
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* helper does not handle driver-specific global state.
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*
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* Similarly to the atomic helpers this function does a complete swap,
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* i.e. it also puts the old state into @state. This is used by the commit
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* code to determine how CDCLK has changed (for instance did it increase or
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* decrease).
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*/
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void intel_cdclk_swap_state(struct intel_atomic_state *state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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swap(state->cdclk_state, dev_priv->cdclk_state);
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}
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void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
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const char *context)
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{
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@ -1904,14 +1873,22 @@ void
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intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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/* called after intel_cdclk_swap_state()! */
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const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
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const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
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const struct intel_cdclk_state *old_cdclk_state =
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intel_atomic_get_old_cdclk_state(state);
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const struct intel_cdclk_state *new_cdclk_state =
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intel_atomic_get_new_cdclk_state(state);
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enum pipe pipe = new_cdclk_state->pipe;
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if (!intel_cdclk_changed(&old_cdclk_state->actual,
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&new_cdclk_state->actual))
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return;
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if (pipe == INVALID_PIPE ||
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old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk)
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old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
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WARN_ON(!new_cdclk_state->base.changed);
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intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
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}
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}
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/**
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@ -1925,14 +1902,22 @@ void
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intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
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{
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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/* called after intel_cdclk_swap_state()! */
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const struct intel_cdclk_state *old_cdclk_state = &state->cdclk_state;
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const struct intel_cdclk_state *new_cdclk_state = &dev_priv->cdclk_state;
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const struct intel_cdclk_state *old_cdclk_state =
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intel_atomic_get_old_cdclk_state(state);
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const struct intel_cdclk_state *new_cdclk_state =
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intel_atomic_get_new_cdclk_state(state);
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enum pipe pipe = new_cdclk_state->pipe;
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if (!intel_cdclk_changed(&old_cdclk_state->actual,
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&new_cdclk_state->actual))
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return;
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if (pipe != INVALID_PIPE &&
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old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk)
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old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
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WARN_ON(!new_cdclk_state->base.changed);
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intel_set_cdclk(dev_priv, &new_cdclk_state->actual, pipe);
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}
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}
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static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
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@ -2059,10 +2044,10 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
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return min_cdclk;
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}
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static int intel_compute_min_cdclk(struct intel_atomic_state *state)
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static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
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{
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struct intel_atomic_state *state = cdclk_state->base.state;
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
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struct intel_crtc *crtc;
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struct intel_crtc_state *crtc_state;
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int min_cdclk, i;
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@ -2080,7 +2065,7 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
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cdclk_state->min_cdclk[i] = min_cdclk;
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ret = _intel_atomic_lock_global_state(state);
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ret = intel_atomic_lock_global_state(&cdclk_state->base);
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if (ret)
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return ret;
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}
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@ -2105,10 +2090,10 @@ static int intel_compute_min_cdclk(struct intel_atomic_state *state)
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* future platforms this code will need to be
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* adjusted.
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*/
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static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
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static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
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{
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struct intel_atomic_state *state = cdclk_state->base.state;
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
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struct intel_crtc *crtc;
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struct intel_crtc_state *crtc_state;
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u8 min_voltage_level;
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@ -2128,7 +2113,7 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
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cdclk_state->min_voltage_level[i] = min_voltage_level;
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ret = _intel_atomic_lock_global_state(state);
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ret = intel_atomic_lock_global_state(&cdclk_state->base);
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if (ret)
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return ret;
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}
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@ -2141,13 +2126,13 @@ static int bxt_compute_min_voltage_level(struct intel_atomic_state *state)
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return min_voltage_level;
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}
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static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
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static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
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{
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struct intel_atomic_state *state = cdclk_state->base.state;
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
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int min_cdclk, cdclk;
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min_cdclk = intel_compute_min_cdclk(state);
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min_cdclk = intel_compute_min_cdclk(cdclk_state);
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if (min_cdclk < 0)
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return min_cdclk;
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@ -2170,12 +2155,12 @@ static int vlv_modeset_calc_cdclk(struct intel_atomic_state *state)
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return 0;
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}
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static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
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static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
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{
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struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
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struct intel_atomic_state *state = cdclk_state->base.state;
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int min_cdclk, cdclk;
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min_cdclk = intel_compute_min_cdclk(state);
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min_cdclk = intel_compute_min_cdclk(cdclk_state);
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if (min_cdclk < 0)
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return min_cdclk;
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@ -2202,10 +2187,10 @@ static int bdw_modeset_calc_cdclk(struct intel_atomic_state *state)
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return 0;
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}
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static int skl_dpll0_vco(struct intel_atomic_state *state)
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static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
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{
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struct intel_atomic_state *state = cdclk_state->base.state;
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
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struct intel_crtc *crtc;
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struct intel_crtc_state *crtc_state;
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int vco, i;
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@ -2239,16 +2224,16 @@ static int skl_dpll0_vco(struct intel_atomic_state *state)
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return vco;
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}
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static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
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static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
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{
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struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
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struct intel_atomic_state *state = cdclk_state->base.state;
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int min_cdclk, cdclk, vco;
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min_cdclk = intel_compute_min_cdclk(state);
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min_cdclk = intel_compute_min_cdclk(cdclk_state);
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if (min_cdclk < 0)
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return min_cdclk;
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vco = skl_dpll0_vco(state);
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vco = skl_dpll0_vco(cdclk_state);
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/*
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* FIXME should also account for plane ratio
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@ -2275,17 +2260,17 @@ static int skl_modeset_calc_cdclk(struct intel_atomic_state *state)
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return 0;
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}
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static int bxt_modeset_calc_cdclk(struct intel_atomic_state *state)
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static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
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{
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struct intel_atomic_state *state = cdclk_state->base.state;
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struct drm_i915_private *dev_priv = to_i915(state->base.dev);
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struct intel_cdclk_state *cdclk_state = &state->cdclk_state;
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||||
int min_cdclk, min_voltage_level, cdclk, vco;
|
||||
|
||||
min_cdclk = intel_compute_min_cdclk(state);
|
||||
min_cdclk = intel_compute_min_cdclk(cdclk_state);
|
||||
if (min_cdclk < 0)
|
||||
return min_cdclk;
|
||||
|
||||
min_voltage_level = bxt_compute_min_voltage_level(state);
|
||||
min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
|
||||
if (min_voltage_level < 0)
|
||||
return min_voltage_level;
|
||||
|
||||
@ -2352,7 +2337,7 @@ static int intel_modeset_all_pipes(struct intel_atomic_state *state)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
|
||||
static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
|
||||
{
|
||||
int min_cdclk;
|
||||
|
||||
@ -2361,54 +2346,95 @@ static int fixed_modeset_calc_cdclk(struct intel_atomic_state *state)
|
||||
* check that the required minimum frequency doesn't exceed
|
||||
* the actual cdclk frequency.
|
||||
*/
|
||||
min_cdclk = intel_compute_min_cdclk(state);
|
||||
min_cdclk = intel_compute_min_cdclk(cdclk_state);
|
||||
if (min_cdclk < 0)
|
||||
return min_cdclk;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
|
||||
{
|
||||
struct intel_cdclk_state *cdclk_state;
|
||||
|
||||
cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
|
||||
if (!cdclk_state)
|
||||
return NULL;
|
||||
|
||||
cdclk_state->force_min_cdclk_changed = false;
|
||||
cdclk_state->pipe = INVALID_PIPE;
|
||||
|
||||
return &cdclk_state->base;
|
||||
}
|
||||
|
||||
static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
|
||||
struct intel_global_state *state)
|
||||
{
|
||||
kfree(state);
|
||||
}
|
||||
|
||||
static const struct intel_global_state_funcs intel_cdclk_funcs = {
|
||||
.atomic_duplicate_state = intel_cdclk_duplicate_state,
|
||||
.atomic_destroy_state = intel_cdclk_destroy_state,
|
||||
};
|
||||
|
||||
struct intel_cdclk_state *
|
||||
intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
struct intel_global_state *cdclk_state;
|
||||
|
||||
cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->cdclk.obj);
|
||||
if (IS_ERR(cdclk_state))
|
||||
return ERR_CAST(cdclk_state);
|
||||
|
||||
return to_intel_cdclk_state(cdclk_state);
|
||||
}
|
||||
|
||||
int intel_cdclk_init(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
struct intel_cdclk_state *cdclk_state;
|
||||
|
||||
cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
|
||||
if (!cdclk_state)
|
||||
return -ENOMEM;
|
||||
|
||||
intel_atomic_global_obj_init(dev_priv, &dev_priv->cdclk.obj,
|
||||
&cdclk_state->base, &intel_cdclk_funcs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
const struct intel_cdclk_state *old_cdclk_state = &dev_priv->cdclk_state;
|
||||
struct intel_cdclk_state *new_cdclk_state = &state->cdclk_state;
|
||||
const struct intel_cdclk_state *old_cdclk_state;
|
||||
struct intel_cdclk_state *new_cdclk_state;
|
||||
enum pipe pipe;
|
||||
int ret;
|
||||
|
||||
memcpy(new_cdclk_state->min_cdclk, old_cdclk_state->min_cdclk,
|
||||
sizeof(new_cdclk_state->min_cdclk));
|
||||
memcpy(new_cdclk_state->min_voltage_level, old_cdclk_state->min_voltage_level,
|
||||
sizeof(new_cdclk_state->min_voltage_level));
|
||||
new_cdclk_state = intel_atomic_get_cdclk_state(state);
|
||||
if (IS_ERR(new_cdclk_state))
|
||||
return PTR_ERR(new_cdclk_state);
|
||||
|
||||
/* keep the current setting */
|
||||
if (!new_cdclk_state->force_min_cdclk_changed)
|
||||
new_cdclk_state->force_min_cdclk = old_cdclk_state->force_min_cdclk;
|
||||
old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
|
||||
|
||||
new_cdclk_state->logical = old_cdclk_state->logical;
|
||||
new_cdclk_state->actual = old_cdclk_state->actual;
|
||||
|
||||
ret = dev_priv->display.modeset_calc_cdclk(state);
|
||||
ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/*
|
||||
* Writes to dev_priv->cdclk.{actual,logical} must protected
|
||||
* by holding all the crtc mutexes even if we don't end up
|
||||
* touching the hardware
|
||||
*/
|
||||
if (intel_cdclk_changed(&old_cdclk_state->actual,
|
||||
&new_cdclk_state->actual)) {
|
||||
/*
|
||||
* Also serialize commits across all crtcs
|
||||
* if the actual hw needs to be poked.
|
||||
*/
|
||||
ret = _intel_atomic_serialize_global_state(state);
|
||||
ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else if (intel_cdclk_changed(&old_cdclk_state->logical,
|
||||
&new_cdclk_state->logical)) {
|
||||
ret = _intel_atomic_lock_global_state(state);
|
||||
ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
|
||||
if (ret)
|
||||
return ret;
|
||||
} else {
|
||||
|
||||
@ -8,11 +8,12 @@
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
#include "i915_drv.h"
|
||||
#include "intel_display.h"
|
||||
#include "intel_global_state.h"
|
||||
|
||||
struct drm_i915_private;
|
||||
struct intel_atomic_state;
|
||||
struct intel_cdclk_config;
|
||||
struct intel_crtc_state;
|
||||
|
||||
struct intel_cdclk_vals {
|
||||
@ -22,6 +23,35 @@ struct intel_cdclk_vals {
|
||||
u8 ratio;
|
||||
};
|
||||
|
||||
struct intel_cdclk_state {
|
||||
struct intel_global_state base;
|
||||
|
||||
/*
|
||||
* Logical configuration of cdclk (used for all scaling,
|
||||
* watermark, etc. calculations and checks). This is
|
||||
* computed as if all enabled crtcs were active.
|
||||
*/
|
||||
struct intel_cdclk_config logical;
|
||||
|
||||
/*
|
||||
* Actual configuration of cdclk, can be different from the
|
||||
* logical configuration only when all crtc's are DPMS off.
|
||||
*/
|
||||
struct intel_cdclk_config actual;
|
||||
|
||||
/* minimum acceptable cdclk for each pipe */
|
||||
int min_cdclk[I915_MAX_PIPES];
|
||||
/* minimum acceptable voltage level for each pipe */
|
||||
u8 min_voltage_level[I915_MAX_PIPES];
|
||||
|
||||
/* pipe to which cd2x update is synchronized */
|
||||
enum pipe pipe;
|
||||
|
||||
/* forced minimum cdclk for glk+ audio w/a */
|
||||
int force_min_cdclk;
|
||||
bool force_min_cdclk_changed;
|
||||
};
|
||||
|
||||
int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state);
|
||||
void intel_cdclk_init_hw(struct drm_i915_private *i915);
|
||||
void intel_cdclk_uninit_hw(struct drm_i915_private *i915);
|
||||
@ -31,12 +61,21 @@ void intel_update_cdclk(struct drm_i915_private *dev_priv);
|
||||
void intel_update_rawclk(struct drm_i915_private *dev_priv);
|
||||
bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
|
||||
const struct intel_cdclk_config *b);
|
||||
void intel_cdclk_clear_state(struct intel_atomic_state *state);
|
||||
void intel_cdclk_swap_state(struct intel_atomic_state *state);
|
||||
void intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state);
|
||||
void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state);
|
||||
void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,
|
||||
const char *context);
|
||||
int intel_modeset_calc_cdclk(struct intel_atomic_state *state);
|
||||
|
||||
struct intel_cdclk_state *
|
||||
intel_atomic_get_cdclk_state(struct intel_atomic_state *state);
|
||||
|
||||
#define to_intel_cdclk_state(x) container_of((x), struct intel_cdclk_state, base)
|
||||
#define intel_atomic_get_old_cdclk_state(state) \
|
||||
to_intel_cdclk_state(intel_atomic_get_old_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
|
||||
#define intel_atomic_get_new_cdclk_state(state) \
|
||||
to_intel_cdclk_state(intel_atomic_get_new_global_obj_state(state, &to_i915(state->base.dev)->cdclk.obj))
|
||||
|
||||
int intel_cdclk_init(struct drm_i915_private *dev_priv);
|
||||
|
||||
#endif /* __INTEL_CDCLK_H__ */
|
||||
|
||||
@ -7532,7 +7532,7 @@ static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
|
||||
struct intel_bw_state *bw_state =
|
||||
to_intel_bw_state(dev_priv->bw_obj.state);
|
||||
struct intel_cdclk_state *cdclk_state =
|
||||
&dev_priv->cdclk_state;
|
||||
to_intel_cdclk_state(dev_priv->cdclk.obj.state);
|
||||
struct intel_crtc_state *crtc_state =
|
||||
to_intel_crtc_state(crtc->base.state);
|
||||
enum intel_display_power_domain domain;
|
||||
@ -7841,17 +7841,17 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
|
||||
return true;
|
||||
}
|
||||
|
||||
static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
|
||||
static int hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
|
||||
{
|
||||
struct drm_i915_private *dev_priv =
|
||||
to_i915(crtc_state->uapi.crtc->dev);
|
||||
struct intel_atomic_state *intel_state =
|
||||
struct intel_atomic_state *state =
|
||||
to_intel_atomic_state(crtc_state->uapi.state);
|
||||
const struct intel_cdclk_state *cdclk_state =
|
||||
&intel_state->cdclk_state;
|
||||
|
||||
crtc_state->ips_enabled = false;
|
||||
|
||||
if (!hsw_crtc_state_ips_capable(crtc_state))
|
||||
return false;
|
||||
return 0;
|
||||
|
||||
/*
|
||||
* When IPS gets enabled, the pipe CRC changes. Since IPS gets
|
||||
@ -7860,18 +7860,27 @@ static bool hsw_compute_ips_config(struct intel_crtc_state *crtc_state)
|
||||
* completely disable it.
|
||||
*/
|
||||
if (crtc_state->crc_enabled)
|
||||
return false;
|
||||
return 0;
|
||||
|
||||
/* IPS should be fine as long as at least one plane is enabled. */
|
||||
if (!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)))
|
||||
return false;
|
||||
return 0;
|
||||
|
||||
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
|
||||
if (IS_BROADWELL(dev_priv) &&
|
||||
crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
|
||||
return false;
|
||||
if (IS_BROADWELL(dev_priv)) {
|
||||
const struct intel_cdclk_state *cdclk_state;
|
||||
|
||||
return true;
|
||||
cdclk_state = intel_atomic_get_cdclk_state(state);
|
||||
if (IS_ERR(cdclk_state))
|
||||
return PTR_ERR(cdclk_state);
|
||||
|
||||
/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
|
||||
if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
|
||||
return 0;
|
||||
}
|
||||
|
||||
crtc_state->ips_enabled = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
|
||||
@ -12686,14 +12695,11 @@ static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
|
||||
adjusted_mode->crtc_clock);
|
||||
}
|
||||
|
||||
static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state)
|
||||
static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
|
||||
const struct intel_cdclk_state *cdclk_state)
|
||||
{
|
||||
const struct intel_atomic_state *state =
|
||||
to_intel_atomic_state(crtc_state->uapi.state);
|
||||
const struct drm_display_mode *adjusted_mode =
|
||||
&crtc_state->hw.adjusted_mode;
|
||||
const struct intel_cdclk_state *cdclk_state =
|
||||
&state->cdclk_state;
|
||||
|
||||
if (!crtc_state->hw.enable)
|
||||
return 0;
|
||||
@ -12723,6 +12729,32 @@ static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
|
||||
return linetime_wm;
|
||||
}
|
||||
|
||||
static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
struct intel_crtc_state *crtc_state =
|
||||
intel_atomic_get_new_crtc_state(state, crtc);
|
||||
const struct intel_cdclk_state *cdclk_state;
|
||||
|
||||
if (INTEL_GEN(dev_priv) >= 9)
|
||||
crtc_state->linetime = skl_linetime_wm(crtc_state);
|
||||
else
|
||||
crtc_state->linetime = hsw_linetime_wm(crtc_state);
|
||||
|
||||
if (!hsw_crtc_supports_ips(crtc))
|
||||
return 0;
|
||||
|
||||
cdclk_state = intel_atomic_get_cdclk_state(state);
|
||||
if (IS_ERR(cdclk_state))
|
||||
return PTR_ERR(cdclk_state);
|
||||
|
||||
crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
|
||||
cdclk_state);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int intel_crtc_atomic_check(struct intel_atomic_state *state,
|
||||
struct intel_crtc *crtc)
|
||||
{
|
||||
@ -12758,7 +12790,6 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = 0;
|
||||
if (dev_priv->display.compute_pipe_wm) {
|
||||
ret = dev_priv->display.compute_pipe_wm(crtc_state);
|
||||
if (ret) {
|
||||
@ -12791,20 +12822,25 @@ static int intel_crtc_atomic_check(struct intel_atomic_state *state,
|
||||
if (!ret)
|
||||
ret = intel_atomic_setup_scalers(dev_priv, crtc,
|
||||
crtc_state);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (HAS_IPS(dev_priv))
|
||||
crtc_state->ips_enabled = hsw_compute_ips_config(crtc_state);
|
||||
|
||||
if (INTEL_GEN(dev_priv) >= 9) {
|
||||
crtc_state->linetime = skl_linetime_wm(crtc_state);
|
||||
} else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
|
||||
crtc_state->linetime = hsw_linetime_wm(crtc_state);
|
||||
if (hsw_crtc_supports_ips(crtc))
|
||||
crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state);
|
||||
if (HAS_IPS(dev_priv)) {
|
||||
ret = hsw_compute_ips_config(crtc_state);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
if (INTEL_GEN(dev_priv) >= 9 ||
|
||||
IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
|
||||
ret = hsw_compute_linetime_wm(state, crtc);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
|
||||
@ -14659,7 +14695,7 @@ static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
|
||||
}
|
||||
|
||||
static int intel_atomic_check_planes(struct intel_atomic_state *state,
|
||||
bool *need_modeset)
|
||||
bool *need_cdclk_calc)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
|
||||
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
|
||||
@ -14714,8 +14750,11 @@ static int intel_atomic_check_planes(struct intel_atomic_state *state,
|
||||
* affected planes are part of the state. We can now
|
||||
* compute the minimum cdclk for each plane.
|
||||
*/
|
||||
for_each_new_intel_plane_in_state(state, plane, plane_state, i)
|
||||
*need_modeset |= intel_plane_calc_min_cdclk(state, plane);
|
||||
for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
|
||||
ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@ -14838,6 +14877,7 @@ static int intel_atomic_check(struct drm_device *dev,
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
struct intel_atomic_state *state = to_intel_atomic_state(_state);
|
||||
struct intel_crtc_state *old_crtc_state, *new_crtc_state;
|
||||
struct intel_cdclk_state *new_cdclk_state;
|
||||
struct intel_crtc *crtc;
|
||||
int ret, i;
|
||||
bool any_ms = false;
|
||||
@ -14953,18 +14993,18 @@ static int intel_atomic_check(struct drm_device *dev,
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
any_ms |= state->cdclk_state.force_min_cdclk_changed;
|
||||
|
||||
ret = intel_atomic_check_planes(state, &any_ms);
|
||||
if (ret)
|
||||
goto fail;
|
||||
|
||||
new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
|
||||
if (new_cdclk_state && new_cdclk_state->force_min_cdclk_changed)
|
||||
any_ms = true;
|
||||
|
||||
if (any_ms) {
|
||||
ret = intel_modeset_checks(state);
|
||||
if (ret)
|
||||
goto fail;
|
||||
} else {
|
||||
state->cdclk_state.logical = dev_priv->cdclk_state.logical;
|
||||
}
|
||||
|
||||
ret = intel_atomic_check_crtcs(state);
|
||||
@ -15866,8 +15906,6 @@ static int intel_atomic_commit(struct drm_device *dev,
|
||||
assert_global_state_locked(dev_priv);
|
||||
|
||||
dev_priv->active_pipes = state->active_pipes;
|
||||
|
||||
intel_cdclk_swap_state(state);
|
||||
}
|
||||
|
||||
drm_atomic_state_get(&state->base);
|
||||
@ -17573,7 +17611,7 @@ void intel_init_display_hooks(struct drm_i915_private *dev_priv)
|
||||
void intel_modeset_init_hw(struct drm_i915_private *i915)
|
||||
{
|
||||
struct intel_cdclk_state *cdclk_state =
|
||||
&i915->cdclk_state;
|
||||
to_intel_cdclk_state(i915->cdclk.obj.state);
|
||||
|
||||
intel_update_cdclk(i915);
|
||||
intel_dump_cdclk_config(&i915->cdclk.hw, "Current CDCLK");
|
||||
@ -17828,6 +17866,10 @@ int intel_modeset_init(struct drm_i915_private *i915)
|
||||
|
||||
intel_mode_config_init(i915);
|
||||
|
||||
ret = intel_cdclk_init(i915);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = intel_bw_init(i915);
|
||||
if (ret)
|
||||
return ret;
|
||||
@ -18318,6 +18360,8 @@ static void readout_plane_state(struct drm_i915_private *dev_priv)
|
||||
static void intel_modeset_readout_hw_state(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
struct intel_cdclk_state *cdclk_state =
|
||||
to_intel_cdclk_state(dev_priv->cdclk.obj.state);
|
||||
enum pipe pipe;
|
||||
struct intel_crtc *crtc;
|
||||
struct intel_encoder *encoder;
|
||||
@ -18441,8 +18485,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
|
||||
for_each_intel_crtc(dev, crtc) {
|
||||
struct intel_bw_state *bw_state =
|
||||
to_intel_bw_state(dev_priv->bw_obj.state);
|
||||
struct intel_cdclk_state *cdclk_state =
|
||||
&dev_priv->cdclk_state;
|
||||
struct intel_crtc_state *crtc_state =
|
||||
to_intel_crtc_state(crtc->base.state);
|
||||
struct intel_plane *plane;
|
||||
|
||||
@ -466,8 +466,6 @@ struct intel_atomic_state {
|
||||
struct __intel_global_objs_state *global_objs;
|
||||
int num_global_objs;
|
||||
|
||||
struct intel_cdclk_state cdclk_state;
|
||||
|
||||
bool dpll_set, modeset;
|
||||
|
||||
/*
|
||||
@ -494,7 +492,6 @@ struct intel_atomic_state {
|
||||
|
||||
/*
|
||||
* active_pipes
|
||||
* cdclk_state
|
||||
*/
|
||||
bool global_state_changed;
|
||||
|
||||
|
||||
@ -65,7 +65,6 @@
|
||||
#include "i915_utils.h"
|
||||
|
||||
#include "display/intel_bios.h"
|
||||
#include "display/intel_cdclk.h"
|
||||
#include "display/intel_display.h"
|
||||
#include "display/intel_display_power.h"
|
||||
#include "display/intel_dpll_mgr.h"
|
||||
@ -256,7 +255,8 @@ struct intel_connector;
|
||||
struct intel_encoder;
|
||||
struct intel_atomic_state;
|
||||
struct intel_cdclk_config;
|
||||
struct intel_crtc_state;
|
||||
struct intel_cdclk_state;
|
||||
struct intel_cdclk_vals;
|
||||
struct intel_initial_plane_config;
|
||||
struct intel_crtc;
|
||||
struct intel_limit;
|
||||
@ -280,7 +280,7 @@ struct drm_i915_display_funcs {
|
||||
struct intel_crtc *crtc);
|
||||
int (*compute_global_watermarks)(struct intel_atomic_state *state);
|
||||
void (*update_wm)(struct intel_crtc *crtc);
|
||||
int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
|
||||
int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
|
||||
u8 (*calc_voltage_level)(int cdclk);
|
||||
/* Returns the active state of the crtc, and if the crtc is active,
|
||||
* fills out the pipe-config with the hw state. */
|
||||
@ -889,33 +889,6 @@ struct i915_selftest_stash {
|
||||
atomic_t counter;
|
||||
};
|
||||
|
||||
struct intel_cdclk_state {
|
||||
/*
|
||||
* Logical configuration of cdclk (used for all scaling,
|
||||
* watermark, etc. calculations and checks). This is
|
||||
* computed as if all enabled crtcs were active.
|
||||
*/
|
||||
struct intel_cdclk_config logical;
|
||||
|
||||
/*
|
||||
* Actual configuration of cdclk, can be different from the
|
||||
* logical configuration only when all crtc's are DPMS off.
|
||||
*/
|
||||
struct intel_cdclk_config actual;
|
||||
|
||||
/* minimum acceptable cdclk for each pipe */
|
||||
int min_cdclk[I915_MAX_PIPES];
|
||||
/* minimum acceptable voltage level for each pipe */
|
||||
u8 min_voltage_level[I915_MAX_PIPES];
|
||||
|
||||
/* pipe to which cd2x update is synchronized */
|
||||
enum pipe pipe;
|
||||
|
||||
/* forced minimum cdclk for glk+ audio w/a */
|
||||
int force_min_cdclk;
|
||||
bool force_min_cdclk_changed;
|
||||
};
|
||||
|
||||
struct drm_i915_private {
|
||||
struct drm_device drm;
|
||||
|
||||
@ -1032,18 +1005,14 @@ struct drm_i915_private {
|
||||
unsigned int fdi_pll_freq;
|
||||
unsigned int czclk_freq;
|
||||
|
||||
/*
|
||||
* For reading holding any crtc lock is sufficient,
|
||||
* for writing must hold all of them.
|
||||
*/
|
||||
struct intel_cdclk_state cdclk_state;
|
||||
|
||||
struct {
|
||||
/* The current hardware cdclk configuration */
|
||||
struct intel_cdclk_config hw;
|
||||
|
||||
/* cdclk, divider, and ratio table from bspec */
|
||||
const struct intel_cdclk_vals *table;
|
||||
|
||||
struct intel_global_obj obj;
|
||||
} cdclk;
|
||||
|
||||
/**
|
||||
@ -1102,8 +1071,8 @@ struct drm_i915_private {
|
||||
struct list_head global_obj_list;
|
||||
|
||||
/*
|
||||
* For reading active_pipes, cdclk_state holding any crtc
|
||||
* lock is sufficient, for writing must hold all of them.
|
||||
* For reading active_pipes holding any crtc lock is
|
||||
* sufficient, for writing must hold all of them.
|
||||
*/
|
||||
u8 active_pipes;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user