mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-20 06:06:57 +07:00
drm/nv50-/disp: rename class members to match nvidia channel names
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
868e34f784
commit
2832271d64
@ -35,8 +35,8 @@
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static struct nouveau_oclass
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gm107_disp_sclass[] = {
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{ GM107_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
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{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
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{ GM107_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
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{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
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{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
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{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
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{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
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@ -44,8 +44,8 @@ gm107_disp_sclass[] = {
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};
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static struct nouveau_oclass
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gm107_disp_base_oclass[] = {
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{ GM107_DISP, &nvd0_disp_base_ofuncs },
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gm107_disp_main_oclass[] = {
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{ GM107_DISP, &nvd0_disp_main_ofuncs },
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{}
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};
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@ -72,7 +72,7 @@ gm107_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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if (ret)
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return ret;
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nv_engine(priv)->sclass = gm107_disp_base_oclass;
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nv_engine(priv)->sclass = gm107_disp_main_oclass;
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nv_engine(priv)->cclass = &nv50_disp_cclass;
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nv_subdev(priv)->intr = nvd0_disp_intr;
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INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
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@ -99,9 +99,9 @@ gm107_disp_oclass = &(struct nv50_disp_impl) {
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},
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.base.vblank = &nvd0_disp_vblank_func,
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.base.outp = nvd0_disp_outp_sclass,
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.mthd.core = &nve0_disp_mast_mthd_chan,
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.mthd.base = &nvd0_disp_sync_mthd_chan,
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.mthd.core = &nve0_disp_core_mthd_chan,
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.mthd.base = &nvd0_disp_base_mthd_chan,
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.mthd.ovly = &nve0_disp_ovly_mthd_chan,
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.mthd.prev = -0x020000,
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.head.scanoutpos = nvd0_disp_base_scanoutpos,
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.head.scanoutpos = nvd0_disp_main_scanoutpos,
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}.base.base;
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@ -35,8 +35,8 @@
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static struct nouveau_oclass
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gm204_disp_sclass[] = {
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{ GM204_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
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{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
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{ GM204_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
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{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
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{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
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{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
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{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
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@ -44,8 +44,8 @@ gm204_disp_sclass[] = {
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};
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static struct nouveau_oclass
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gm204_disp_base_oclass[] = {
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{ GM204_DISP, &nvd0_disp_base_ofuncs },
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gm204_disp_main_oclass[] = {
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{ GM204_DISP, &nvd0_disp_main_ofuncs },
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{}
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};
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@ -72,7 +72,7 @@ gm204_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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if (ret)
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return ret;
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nv_engine(priv)->sclass = gm204_disp_base_oclass;
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nv_engine(priv)->sclass = gm204_disp_main_oclass;
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nv_engine(priv)->cclass = &nv50_disp_cclass;
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nv_subdev(priv)->intr = nvd0_disp_intr;
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INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
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@ -106,9 +106,9 @@ gm204_disp_oclass = &(struct nv50_disp_impl) {
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},
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.base.vblank = &nvd0_disp_vblank_func,
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.base.outp = gm204_disp_outp_sclass,
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.mthd.core = &nve0_disp_mast_mthd_chan,
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.mthd.base = &nvd0_disp_sync_mthd_chan,
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.mthd.core = &nve0_disp_core_mthd_chan,
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.mthd.base = &nvd0_disp_base_mthd_chan,
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.mthd.ovly = &nve0_disp_ovly_mthd_chan,
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.mthd.prev = -0x020000,
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.head.scanoutpos = nvd0_disp_base_scanoutpos,
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.head.scanoutpos = nvd0_disp_main_scanoutpos,
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}.base.base;
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@ -374,7 +374,7 @@ nv50_disp_mthd_chan(struct nv50_disp_priv *priv, int debug, int head,
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}
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const struct nv50_disp_mthd_list
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nv50_disp_mast_mthd_base = {
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nv50_disp_core_mthd_base = {
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.mthd = 0x0000,
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.addr = 0x000000,
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.data = {
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@ -387,7 +387,7 @@ nv50_disp_mast_mthd_base = {
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};
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static const struct nv50_disp_mthd_list
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nv50_disp_mast_mthd_dac = {
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nv50_disp_core_mthd_dac = {
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.mthd = 0x0080,
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.addr = 0x000008,
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.data = {
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@ -399,7 +399,7 @@ nv50_disp_mast_mthd_dac = {
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};
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const struct nv50_disp_mthd_list
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nv50_disp_mast_mthd_sor = {
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nv50_disp_core_mthd_sor = {
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.mthd = 0x0040,
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.addr = 0x000008,
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.data = {
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@ -409,7 +409,7 @@ nv50_disp_mast_mthd_sor = {
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};
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const struct nv50_disp_mthd_list
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nv50_disp_mast_mthd_pior = {
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nv50_disp_core_mthd_pior = {
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.mthd = 0x0040,
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.addr = 0x000008,
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.data = {
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@ -419,7 +419,7 @@ nv50_disp_mast_mthd_pior = {
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};
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static const struct nv50_disp_mthd_list
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nv50_disp_mast_mthd_head = {
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nv50_disp_core_mthd_head = {
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.mthd = 0x0400,
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.addr = 0x000540,
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.data = {
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@ -466,21 +466,21 @@ nv50_disp_mast_mthd_head = {
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};
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static const struct nv50_disp_mthd_chan
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nv50_disp_mast_mthd_chan = {
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nv50_disp_core_mthd_chan = {
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.name = "Core",
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.addr = 0x000000,
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.data = {
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{ "Global", 1, &nv50_disp_mast_mthd_base },
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{ "DAC", 3, &nv50_disp_mast_mthd_dac },
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{ "SOR", 2, &nv50_disp_mast_mthd_sor },
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{ "PIOR", 3, &nv50_disp_mast_mthd_pior },
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{ "HEAD", 2, &nv50_disp_mast_mthd_head },
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{ "Global", 1, &nv50_disp_core_mthd_base },
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{ "DAC", 3, &nv50_disp_core_mthd_dac },
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{ "SOR", 2, &nv50_disp_core_mthd_sor },
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{ "PIOR", 3, &nv50_disp_core_mthd_pior },
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{ "HEAD", 2, &nv50_disp_core_mthd_head },
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{}
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}
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};
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int
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nv50_disp_mast_ctor(struct nouveau_object *parent,
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nv50_disp_core_ctor(struct nouveau_object *parent,
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struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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@ -509,7 +509,7 @@ nv50_disp_mast_ctor(struct nouveau_object *parent,
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}
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static int
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nv50_disp_mast_init(struct nouveau_object *object)
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nv50_disp_core_init(struct nouveau_object *object)
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{
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struct nv50_disp_priv *priv = (void *)object->engine;
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struct nv50_disp_dmac *mast = (void *)object;
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@ -546,7 +546,7 @@ nv50_disp_mast_init(struct nouveau_object *object)
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}
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static int
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nv50_disp_mast_fini(struct nouveau_object *object, bool suspend)
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nv50_disp_core_fini(struct nouveau_object *object, bool suspend)
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{
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struct nv50_disp_priv *priv = (void *)object->engine;
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struct nv50_disp_dmac *mast = (void *)object;
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@ -567,11 +567,11 @@ nv50_disp_mast_fini(struct nouveau_object *object, bool suspend)
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}
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struct nv50_disp_chan_impl
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nv50_disp_mast_ofuncs = {
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.base.ctor = nv50_disp_mast_ctor,
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nv50_disp_core_ofuncs = {
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.base.ctor = nv50_disp_core_ctor,
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.base.dtor = nv50_disp_dmac_dtor,
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.base.init = nv50_disp_mast_init,
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.base.fini = nv50_disp_mast_fini,
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.base.init = nv50_disp_core_init,
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.base.fini = nv50_disp_core_fini,
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.base.map = nv50_disp_chan_map,
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.base.ntfy = nv50_disp_chan_ntfy,
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.base.rd32 = nv50_disp_chan_rd32,
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@ -586,7 +586,7 @@ nv50_disp_mast_ofuncs = {
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******************************************************************************/
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static const struct nv50_disp_mthd_list
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nv50_disp_sync_mthd_base = {
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nv50_disp_base_mthd_base = {
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.mthd = 0x0000,
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.addr = 0x000000,
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.data = {
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@ -611,7 +611,7 @@ nv50_disp_sync_mthd_base = {
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};
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const struct nv50_disp_mthd_list
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nv50_disp_sync_mthd_image = {
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nv50_disp_base_mthd_image = {
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.mthd = 0x0400,
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.addr = 0x000000,
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.data = {
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@ -625,18 +625,18 @@ nv50_disp_sync_mthd_image = {
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};
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static const struct nv50_disp_mthd_chan
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nv50_disp_sync_mthd_chan = {
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nv50_disp_base_mthd_chan = {
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.name = "Base",
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.addr = 0x000540,
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.data = {
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{ "Global", 1, &nv50_disp_sync_mthd_base },
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{ "Image", 2, &nv50_disp_sync_mthd_image },
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{ "Global", 1, &nv50_disp_base_mthd_base },
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{ "Image", 2, &nv50_disp_base_mthd_image },
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{}
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}
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};
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int
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nv50_disp_sync_ctor(struct nouveau_object *parent,
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nv50_disp_base_ctor(struct nouveau_object *parent,
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struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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@ -669,8 +669,8 @@ nv50_disp_sync_ctor(struct nouveau_object *parent,
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}
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struct nv50_disp_chan_impl
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nv50_disp_sync_ofuncs = {
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.base.ctor = nv50_disp_sync_ctor,
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nv50_disp_base_ofuncs = {
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.base.ctor = nv50_disp_base_ctor,
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.base.dtor = nv50_disp_dmac_dtor,
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.base.init = nv50_disp_dmac_init,
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.base.fini = nv50_disp_dmac_fini,
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@ -942,7 +942,7 @@ nv50_disp_curs_ofuncs = {
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******************************************************************************/
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int
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nv50_disp_base_scanoutpos(NV50_DISP_MTHD_V0)
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nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0)
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{
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const u32 blanke = nv_rd32(priv, 0x610aec + (head * 0x540));
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const u32 blanks = nv_rd32(priv, 0x610af4 + (head * 0x540));
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@ -974,7 +974,7 @@ nv50_disp_base_scanoutpos(NV50_DISP_MTHD_V0)
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}
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int
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nv50_disp_base_mthd(struct nouveau_object *object, u32 mthd,
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nv50_disp_main_mthd(struct nouveau_object *object, u32 mthd,
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void *data, u32 size)
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{
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const struct nv50_disp_impl *impl = (void *)nv_oclass(object->engine);
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@ -1098,7 +1098,7 @@ nv50_disp_base_mthd(struct nouveau_object *object, u32 mthd,
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}
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int
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nv50_disp_base_ctor(struct nouveau_object *parent,
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nv50_disp_main_ctor(struct nouveau_object *parent,
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struct nouveau_object *engine,
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struct nouveau_oclass *oclass, void *data, u32 size,
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struct nouveau_object **pobject)
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@ -1118,7 +1118,7 @@ nv50_disp_base_ctor(struct nouveau_object *parent,
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}
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void
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nv50_disp_base_dtor(struct nouveau_object *object)
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nv50_disp_main_dtor(struct nouveau_object *object)
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{
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struct nv50_disp_base *base = (void *)object;
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nouveau_ramht_ref(NULL, &base->ramht);
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@ -1126,7 +1126,7 @@ nv50_disp_base_dtor(struct nouveau_object *object)
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}
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static int
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nv50_disp_base_init(struct nouveau_object *object)
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nv50_disp_main_init(struct nouveau_object *object)
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{
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struct nv50_disp_priv *priv = (void *)object->engine;
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struct nv50_disp_base *base = (void *)object;
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@ -1194,7 +1194,7 @@ nv50_disp_base_init(struct nouveau_object *object)
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}
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static int
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nv50_disp_base_fini(struct nouveau_object *object, bool suspend)
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nv50_disp_main_fini(struct nouveau_object *object, bool suspend)
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{
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struct nv50_disp_priv *priv = (void *)object->engine;
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struct nv50_disp_base *base = (void *)object;
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@ -1207,25 +1207,25 @@ nv50_disp_base_fini(struct nouveau_object *object, bool suspend)
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}
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struct nouveau_ofuncs
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nv50_disp_base_ofuncs = {
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.ctor = nv50_disp_base_ctor,
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.dtor = nv50_disp_base_dtor,
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.init = nv50_disp_base_init,
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.fini = nv50_disp_base_fini,
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.mthd = nv50_disp_base_mthd,
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nv50_disp_main_ofuncs = {
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.ctor = nv50_disp_main_ctor,
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.dtor = nv50_disp_main_dtor,
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.init = nv50_disp_main_init,
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.fini = nv50_disp_main_fini,
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.mthd = nv50_disp_main_mthd,
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.ntfy = nouveau_disp_ntfy,
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};
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static struct nouveau_oclass
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nv50_disp_base_oclass[] = {
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{ NV50_DISP, &nv50_disp_base_ofuncs },
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nv50_disp_main_oclass[] = {
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{ NV50_DISP, &nv50_disp_main_ofuncs },
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{}
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};
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static struct nouveau_oclass
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nv50_disp_sclass[] = {
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{ NV50_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
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{ NV50_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
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{ NV50_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
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{ NV50_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
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{ NV50_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
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{ NV50_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
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{ NV50_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
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@ -1974,7 +1974,7 @@ nv50_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
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if (ret)
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return ret;
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nv_engine(priv)->sclass = nv50_disp_base_oclass;
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nv_engine(priv)->sclass = nv50_disp_main_oclass;
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nv_engine(priv)->cclass = &nv50_disp_cclass;
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nv_subdev(priv)->intr = nv50_disp_intr;
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INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
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@ -2007,9 +2007,9 @@ nv50_disp_oclass = &(struct nv50_disp_impl) {
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},
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.base.vblank = &nv50_disp_vblank_func,
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.base.outp = nv50_disp_outp_sclass,
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.mthd.core = &nv50_disp_mast_mthd_chan,
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.mthd.base = &nv50_disp_sync_mthd_chan,
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.mthd.core = &nv50_disp_core_mthd_chan,
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.mthd.base = &nv50_disp_base_mthd_chan,
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.mthd.ovly = &nv50_disp_ovly_mthd_chan,
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.mthd.prev = 0x000004,
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.head.scanoutpos = nv50_disp_base_scanoutpos,
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.head.scanoutpos = nv50_disp_main_scanoutpos,
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}.base.base;
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@ -64,10 +64,10 @@ struct nv50_disp_impl {
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} head;
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};
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int nv50_disp_base_scanoutpos(NV50_DISP_MTHD_V0);
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int nv50_disp_base_mthd(struct nouveau_object *, u32, void *, u32);
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int nv50_disp_main_scanoutpos(NV50_DISP_MTHD_V0);
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int nv50_disp_main_mthd(struct nouveau_object *, u32, void *, u32);
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|
||||
int nvd0_disp_base_scanoutpos(NV50_DISP_MTHD_V0);
|
||||
int nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0);
|
||||
|
||||
int nv50_dac_power(NV50_DISP_MTHD_V1);
|
||||
int nv50_dac_sense(NV50_DISP_MTHD_V1);
|
||||
@ -170,18 +170,18 @@ struct nv50_disp_mthd_chan {
|
||||
} data[];
|
||||
};
|
||||
|
||||
extern struct nv50_disp_chan_impl nv50_disp_mast_ofuncs;
|
||||
int nv50_disp_mast_ctor(struct nouveau_object *, struct nouveau_object *,
|
||||
extern struct nv50_disp_chan_impl nv50_disp_core_ofuncs;
|
||||
int nv50_disp_core_ctor(struct nouveau_object *, struct nouveau_object *,
|
||||
struct nouveau_oclass *, void *, u32,
|
||||
struct nouveau_object **);
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_base;
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_sor;
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_mast_mthd_pior;
|
||||
extern struct nv50_disp_chan_impl nv50_disp_sync_ofuncs;
|
||||
int nv50_disp_sync_ctor(struct nouveau_object *, struct nouveau_object *,
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_base;
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_sor;
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_core_mthd_pior;
|
||||
extern struct nv50_disp_chan_impl nv50_disp_base_ofuncs;
|
||||
int nv50_disp_base_ctor(struct nouveau_object *, struct nouveau_object *,
|
||||
struct nouveau_oclass *, void *, u32,
|
||||
struct nouveau_object **);
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_sync_mthd_image;
|
||||
extern const struct nv50_disp_mthd_list nv50_disp_base_mthd_image;
|
||||
extern struct nv50_disp_chan_impl nv50_disp_ovly_ofuncs;
|
||||
int nv50_disp_ovly_ctor(struct nouveau_object *, struct nouveau_object *,
|
||||
struct nouveau_oclass *, void *, u32,
|
||||
@ -195,12 +195,12 @@ extern struct nv50_disp_chan_impl nv50_disp_curs_ofuncs;
|
||||
int nv50_disp_curs_ctor(struct nouveau_object *, struct nouveau_object *,
|
||||
struct nouveau_oclass *, void *, u32,
|
||||
struct nouveau_object **);
|
||||
extern struct nouveau_ofuncs nv50_disp_base_ofuncs;
|
||||
int nv50_disp_base_ctor(struct nouveau_object *, struct nouveau_object *,
|
||||
extern struct nouveau_ofuncs nv50_disp_main_ofuncs;
|
||||
int nv50_disp_main_ctor(struct nouveau_object *, struct nouveau_object *,
|
||||
struct nouveau_oclass *, void *, u32,
|
||||
struct nouveau_object **);
|
||||
void nv50_disp_base_dtor(struct nouveau_object *);
|
||||
extern struct nouveau_omthds nv50_disp_base_omthds[];
|
||||
void nv50_disp_main_dtor(struct nouveau_object *);
|
||||
extern struct nouveau_omthds nv50_disp_main_omthds[];
|
||||
extern struct nouveau_oclass nv50_disp_cclass;
|
||||
void nv50_disp_mthd_chan(struct nv50_disp_priv *, int debug, int head,
|
||||
const struct nv50_disp_mthd_chan *);
|
||||
@ -208,31 +208,31 @@ void nv50_disp_intr_supervisor(struct work_struct *);
|
||||
void nv50_disp_intr(struct nouveau_subdev *);
|
||||
extern const struct nvkm_event_func nv50_disp_vblank_func;
|
||||
|
||||
extern const struct nv50_disp_mthd_chan nv84_disp_mast_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_list nv84_disp_mast_mthd_dac;
|
||||
extern const struct nv50_disp_mthd_list nv84_disp_mast_mthd_head;
|
||||
extern const struct nv50_disp_mthd_chan nv84_disp_sync_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_chan nv84_disp_core_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_list nv84_disp_core_mthd_dac;
|
||||
extern const struct nv50_disp_mthd_list nv84_disp_core_mthd_head;
|
||||
extern const struct nv50_disp_mthd_chan nv84_disp_base_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_chan nv84_disp_ovly_mthd_chan;
|
||||
|
||||
extern const struct nv50_disp_mthd_chan nv94_disp_mast_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_chan nv94_disp_core_mthd_chan;
|
||||
|
||||
extern struct nv50_disp_chan_impl nvd0_disp_mast_ofuncs;
|
||||
extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_base;
|
||||
extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_dac;
|
||||
extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_sor;
|
||||
extern const struct nv50_disp_mthd_list nvd0_disp_mast_mthd_pior;
|
||||
extern struct nv50_disp_chan_impl nvd0_disp_sync_ofuncs;
|
||||
extern struct nv50_disp_chan_impl nvd0_disp_core_ofuncs;
|
||||
extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_base;
|
||||
extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_dac;
|
||||
extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_sor;
|
||||
extern const struct nv50_disp_mthd_list nvd0_disp_core_mthd_pior;
|
||||
extern struct nv50_disp_chan_impl nvd0_disp_base_ofuncs;
|
||||
extern struct nv50_disp_chan_impl nvd0_disp_ovly_ofuncs;
|
||||
extern const struct nv50_disp_mthd_chan nvd0_disp_sync_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_chan nvd0_disp_base_mthd_chan;
|
||||
extern struct nv50_disp_chan_impl nvd0_disp_oimm_ofuncs;
|
||||
extern struct nv50_disp_chan_impl nvd0_disp_curs_ofuncs;
|
||||
extern struct nouveau_ofuncs nvd0_disp_base_ofuncs;
|
||||
extern struct nouveau_ofuncs nvd0_disp_main_ofuncs;
|
||||
extern struct nouveau_oclass nvd0_disp_cclass;
|
||||
void nvd0_disp_intr_supervisor(struct work_struct *);
|
||||
void nvd0_disp_intr(struct nouveau_subdev *);
|
||||
extern const struct nvkm_event_func nvd0_disp_vblank_func;
|
||||
|
||||
extern const struct nv50_disp_mthd_chan nve0_disp_mast_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_chan nve0_disp_core_mthd_chan;
|
||||
extern const struct nv50_disp_mthd_chan nve0_disp_ovly_mthd_chan;
|
||||
|
||||
extern struct nvkm_output_dp_impl nv50_pior_dp_impl;
|
||||
|
||||
@ -34,7 +34,7 @@
|
||||
******************************************************************************/
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
nv84_disp_mast_mthd_dac = {
|
||||
nv84_disp_core_mthd_dac = {
|
||||
.mthd = 0x0080,
|
||||
.addr = 0x000008,
|
||||
.data = {
|
||||
@ -46,7 +46,7 @@ nv84_disp_mast_mthd_dac = {
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
nv84_disp_mast_mthd_head = {
|
||||
nv84_disp_core_mthd_head = {
|
||||
.mthd = 0x0400,
|
||||
.addr = 0x000540,
|
||||
.data = {
|
||||
@ -98,15 +98,15 @@ nv84_disp_mast_mthd_head = {
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
nv84_disp_mast_mthd_chan = {
|
||||
nv84_disp_core_mthd_chan = {
|
||||
.name = "Core",
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ "Global", 1, &nv50_disp_mast_mthd_base },
|
||||
{ "DAC", 3, &nv84_disp_mast_mthd_dac },
|
||||
{ "SOR", 2, &nv50_disp_mast_mthd_sor },
|
||||
{ "PIOR", 3, &nv50_disp_mast_mthd_pior },
|
||||
{ "HEAD", 2, &nv84_disp_mast_mthd_head },
|
||||
{ "Global", 1, &nv50_disp_core_mthd_base },
|
||||
{ "DAC", 3, &nv84_disp_core_mthd_dac },
|
||||
{ "SOR", 2, &nv50_disp_core_mthd_sor },
|
||||
{ "PIOR", 3, &nv50_disp_core_mthd_pior },
|
||||
{ "HEAD", 2, &nv84_disp_core_mthd_head },
|
||||
{}
|
||||
}
|
||||
};
|
||||
@ -116,7 +116,7 @@ nv84_disp_mast_mthd_chan = {
|
||||
******************************************************************************/
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
nv84_disp_sync_mthd_base = {
|
||||
nv84_disp_base_mthd_base = {
|
||||
.mthd = 0x0000,
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
@ -146,12 +146,12 @@ nv84_disp_sync_mthd_base = {
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
nv84_disp_sync_mthd_chan = {
|
||||
nv84_disp_base_mthd_chan = {
|
||||
.name = "Base",
|
||||
.addr = 0x000540,
|
||||
.data = {
|
||||
{ "Global", 1, &nv84_disp_sync_mthd_base },
|
||||
{ "Image", 2, &nv50_disp_sync_mthd_image },
|
||||
{ "Global", 1, &nv84_disp_base_mthd_base },
|
||||
{ "Image", 2, &nv50_disp_base_mthd_image },
|
||||
{}
|
||||
}
|
||||
};
|
||||
@ -204,8 +204,8 @@ nv84_disp_ovly_mthd_chan = {
|
||||
|
||||
static struct nouveau_oclass
|
||||
nv84_disp_sclass[] = {
|
||||
{ G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
|
||||
{ G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
|
||||
{ G82_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
|
||||
{ G82_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
|
||||
{ G82_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
|
||||
{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
|
||||
{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
|
||||
@ -213,8 +213,8 @@ nv84_disp_sclass[] = {
|
||||
};
|
||||
|
||||
static struct nouveau_oclass
|
||||
nv84_disp_base_oclass[] = {
|
||||
{ G82_DISP, &nv50_disp_base_ofuncs },
|
||||
nv84_disp_main_oclass[] = {
|
||||
{ G82_DISP, &nv50_disp_main_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
@ -240,7 +240,7 @@ nv84_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(priv)->sclass = nv84_disp_base_oclass;
|
||||
nv_engine(priv)->sclass = nv84_disp_main_oclass;
|
||||
nv_engine(priv)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(priv)->intr = nv50_disp_intr;
|
||||
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
|
||||
@ -268,9 +268,9 @@ nv84_disp_oclass = &(struct nv50_disp_impl) {
|
||||
},
|
||||
.base.vblank = &nv50_disp_vblank_func,
|
||||
.base.outp = nv50_disp_outp_sclass,
|
||||
.mthd.core = &nv84_disp_mast_mthd_chan,
|
||||
.mthd.base = &nv84_disp_sync_mthd_chan,
|
||||
.mthd.core = &nv84_disp_core_mthd_chan,
|
||||
.mthd.base = &nv84_disp_base_mthd_chan,
|
||||
.mthd.ovly = &nv84_disp_ovly_mthd_chan,
|
||||
.mthd.prev = 0x000004,
|
||||
.head.scanoutpos = nv50_disp_base_scanoutpos,
|
||||
.head.scanoutpos = nv50_disp_main_scanoutpos,
|
||||
}.base.base;
|
||||
|
||||
@ -34,7 +34,7 @@
|
||||
******************************************************************************/
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
nv94_disp_mast_mthd_sor = {
|
||||
nv94_disp_core_mthd_sor = {
|
||||
.mthd = 0x0040,
|
||||
.addr = 0x000008,
|
||||
.data = {
|
||||
@ -44,15 +44,15 @@ nv94_disp_mast_mthd_sor = {
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
nv94_disp_mast_mthd_chan = {
|
||||
nv94_disp_core_mthd_chan = {
|
||||
.name = "Core",
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ "Global", 1, &nv50_disp_mast_mthd_base },
|
||||
{ "DAC", 3, &nv84_disp_mast_mthd_dac },
|
||||
{ "SOR", 4, &nv94_disp_mast_mthd_sor },
|
||||
{ "PIOR", 3, &nv50_disp_mast_mthd_pior },
|
||||
{ "HEAD", 2, &nv84_disp_mast_mthd_head },
|
||||
{ "Global", 1, &nv50_disp_core_mthd_base },
|
||||
{ "DAC", 3, &nv84_disp_core_mthd_dac },
|
||||
{ "SOR", 4, &nv94_disp_core_mthd_sor },
|
||||
{ "PIOR", 3, &nv50_disp_core_mthd_pior },
|
||||
{ "HEAD", 2, &nv84_disp_core_mthd_head },
|
||||
{}
|
||||
}
|
||||
};
|
||||
@ -63,8 +63,8 @@ nv94_disp_mast_mthd_chan = {
|
||||
|
||||
static struct nouveau_oclass
|
||||
nv94_disp_sclass[] = {
|
||||
{ GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
|
||||
{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
|
||||
{ GT206_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
|
||||
{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
|
||||
{ GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
|
||||
{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
|
||||
{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
|
||||
@ -72,8 +72,8 @@ nv94_disp_sclass[] = {
|
||||
};
|
||||
|
||||
static struct nouveau_oclass
|
||||
nv94_disp_base_oclass[] = {
|
||||
{ GT206_DISP, &nv50_disp_base_ofuncs },
|
||||
nv94_disp_main_oclass[] = {
|
||||
{ GT206_DISP, &nv50_disp_main_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
@ -99,7 +99,7 @@ nv94_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(priv)->sclass = nv94_disp_base_oclass;
|
||||
nv_engine(priv)->sclass = nv94_disp_main_oclass;
|
||||
nv_engine(priv)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(priv)->intr = nv50_disp_intr;
|
||||
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
|
||||
@ -134,9 +134,9 @@ nv94_disp_oclass = &(struct nv50_disp_impl) {
|
||||
},
|
||||
.base.vblank = &nv50_disp_vblank_func,
|
||||
.base.outp = nv94_disp_outp_sclass,
|
||||
.mthd.core = &nv94_disp_mast_mthd_chan,
|
||||
.mthd.base = &nv84_disp_sync_mthd_chan,
|
||||
.mthd.core = &nv94_disp_core_mthd_chan,
|
||||
.mthd.base = &nv84_disp_base_mthd_chan,
|
||||
.mthd.ovly = &nv84_disp_ovly_mthd_chan,
|
||||
.mthd.prev = 0x000004,
|
||||
.head.scanoutpos = nv50_disp_base_scanoutpos,
|
||||
.head.scanoutpos = nv50_disp_main_scanoutpos,
|
||||
}.base.base;
|
||||
|
||||
@ -80,8 +80,8 @@ nva0_disp_ovly_mthd_chan = {
|
||||
|
||||
static struct nouveau_oclass
|
||||
nva0_disp_sclass[] = {
|
||||
{ GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
|
||||
{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
|
||||
{ GT200_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
|
||||
{ GT200_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
|
||||
{ GT200_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
|
||||
{ G82_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
|
||||
{ G82_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
|
||||
@ -89,8 +89,8 @@ nva0_disp_sclass[] = {
|
||||
};
|
||||
|
||||
static struct nouveau_oclass
|
||||
nva0_disp_base_oclass[] = {
|
||||
{ GT200_DISP, &nv50_disp_base_ofuncs },
|
||||
nva0_disp_main_oclass[] = {
|
||||
{ GT200_DISP, &nv50_disp_main_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
@ -116,7 +116,7 @@ nva0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(priv)->sclass = nva0_disp_base_oclass;
|
||||
nv_engine(priv)->sclass = nva0_disp_main_oclass;
|
||||
nv_engine(priv)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(priv)->intr = nv50_disp_intr;
|
||||
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
|
||||
@ -144,9 +144,9 @@ nva0_disp_oclass = &(struct nv50_disp_impl) {
|
||||
},
|
||||
.base.vblank = &nv50_disp_vblank_func,
|
||||
.base.outp = nv50_disp_outp_sclass,
|
||||
.mthd.core = &nv84_disp_mast_mthd_chan,
|
||||
.mthd.base = &nv84_disp_sync_mthd_chan,
|
||||
.mthd.core = &nv84_disp_core_mthd_chan,
|
||||
.mthd.base = &nv84_disp_base_mthd_chan,
|
||||
.mthd.ovly = &nva0_disp_ovly_mthd_chan,
|
||||
.mthd.prev = 0x000004,
|
||||
.head.scanoutpos = nv50_disp_base_scanoutpos,
|
||||
.head.scanoutpos = nv50_disp_main_scanoutpos,
|
||||
}.base.base;
|
||||
|
||||
@ -35,8 +35,8 @@
|
||||
|
||||
static struct nouveau_oclass
|
||||
nva3_disp_sclass[] = {
|
||||
{ GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_mast_ofuncs.base },
|
||||
{ GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_sync_ofuncs.base },
|
||||
{ GT214_DISP_CORE_CHANNEL_DMA, &nv50_disp_core_ofuncs.base },
|
||||
{ GT214_DISP_BASE_CHANNEL_DMA, &nv50_disp_base_ofuncs.base },
|
||||
{ GT214_DISP_OVERLAY_CHANNEL_DMA, &nv50_disp_ovly_ofuncs.base },
|
||||
{ GT214_DISP_OVERLAY, &nv50_disp_oimm_ofuncs.base },
|
||||
{ GT214_DISP_CURSOR, &nv50_disp_curs_ofuncs.base },
|
||||
@ -44,8 +44,8 @@ nva3_disp_sclass[] = {
|
||||
};
|
||||
|
||||
static struct nouveau_oclass
|
||||
nva3_disp_base_oclass[] = {
|
||||
{ GT214_DISP, &nv50_disp_base_ofuncs },
|
||||
nva3_disp_main_oclass[] = {
|
||||
{ GT214_DISP, &nv50_disp_main_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
@ -71,7 +71,7 @@ nva3_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(priv)->sclass = nva3_disp_base_oclass;
|
||||
nv_engine(priv)->sclass = nva3_disp_main_oclass;
|
||||
nv_engine(priv)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(priv)->intr = nv50_disp_intr;
|
||||
INIT_WORK(&priv->supervisor, nv50_disp_intr_supervisor);
|
||||
@ -100,9 +100,9 @@ nva3_disp_oclass = &(struct nv50_disp_impl) {
|
||||
},
|
||||
.base.vblank = &nv50_disp_vblank_func,
|
||||
.base.outp = nv94_disp_outp_sclass,
|
||||
.mthd.core = &nv94_disp_mast_mthd_chan,
|
||||
.mthd.base = &nv84_disp_sync_mthd_chan,
|
||||
.mthd.core = &nv94_disp_core_mthd_chan,
|
||||
.mthd.base = &nv84_disp_base_mthd_chan,
|
||||
.mthd.ovly = &nv84_disp_ovly_mthd_chan,
|
||||
.mthd.prev = 0x000004,
|
||||
.head.scanoutpos = nv50_disp_base_scanoutpos,
|
||||
.head.scanoutpos = nv50_disp_main_scanoutpos,
|
||||
}.base.base;
|
||||
|
||||
@ -151,7 +151,7 @@ nvd0_disp_dmac_fini(struct nouveau_object *object, bool suspend)
|
||||
******************************************************************************/
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
nvd0_disp_mast_mthd_base = {
|
||||
nvd0_disp_core_mthd_base = {
|
||||
.mthd = 0x0000,
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
@ -164,7 +164,7 @@ nvd0_disp_mast_mthd_base = {
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
nvd0_disp_mast_mthd_dac = {
|
||||
nvd0_disp_core_mthd_dac = {
|
||||
.mthd = 0x0020,
|
||||
.addr = 0x000020,
|
||||
.data = {
|
||||
@ -177,7 +177,7 @@ nvd0_disp_mast_mthd_dac = {
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
nvd0_disp_mast_mthd_sor = {
|
||||
nvd0_disp_core_mthd_sor = {
|
||||
.mthd = 0x0020,
|
||||
.addr = 0x000020,
|
||||
.data = {
|
||||
@ -190,7 +190,7 @@ nvd0_disp_mast_mthd_sor = {
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_list
|
||||
nvd0_disp_mast_mthd_pior = {
|
||||
nvd0_disp_core_mthd_pior = {
|
||||
.mthd = 0x0020,
|
||||
.addr = 0x000020,
|
||||
.data = {
|
||||
@ -203,7 +203,7 @@ nvd0_disp_mast_mthd_pior = {
|
||||
};
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
nvd0_disp_mast_mthd_head = {
|
||||
nvd0_disp_core_mthd_head = {
|
||||
.mthd = 0x0300,
|
||||
.addr = 0x000300,
|
||||
.data = {
|
||||
@ -277,21 +277,21 @@ nvd0_disp_mast_mthd_head = {
|
||||
};
|
||||
|
||||
static const struct nv50_disp_mthd_chan
|
||||
nvd0_disp_mast_mthd_chan = {
|
||||
nvd0_disp_core_mthd_chan = {
|
||||
.name = "Core",
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ "Global", 1, &nvd0_disp_mast_mthd_base },
|
||||
{ "DAC", 3, &nvd0_disp_mast_mthd_dac },
|
||||
{ "SOR", 8, &nvd0_disp_mast_mthd_sor },
|
||||
{ "PIOR", 4, &nvd0_disp_mast_mthd_pior },
|
||||
{ "HEAD", 4, &nvd0_disp_mast_mthd_head },
|
||||
{ "Global", 1, &nvd0_disp_core_mthd_base },
|
||||
{ "DAC", 3, &nvd0_disp_core_mthd_dac },
|
||||
{ "SOR", 8, &nvd0_disp_core_mthd_sor },
|
||||
{ "PIOR", 4, &nvd0_disp_core_mthd_pior },
|
||||
{ "HEAD", 4, &nvd0_disp_core_mthd_head },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
static int
|
||||
nvd0_disp_mast_init(struct nouveau_object *object)
|
||||
nvd0_disp_core_init(struct nouveau_object *object)
|
||||
{
|
||||
struct nv50_disp_priv *priv = (void *)object->engine;
|
||||
struct nv50_disp_dmac *mast = (void *)object;
|
||||
@ -322,7 +322,7 @@ nvd0_disp_mast_init(struct nouveau_object *object)
|
||||
}
|
||||
|
||||
static int
|
||||
nvd0_disp_mast_fini(struct nouveau_object *object, bool suspend)
|
||||
nvd0_disp_core_fini(struct nouveau_object *object, bool suspend)
|
||||
{
|
||||
struct nv50_disp_priv *priv = (void *)object->engine;
|
||||
struct nv50_disp_dmac *mast = (void *)object;
|
||||
@ -344,11 +344,11 @@ nvd0_disp_mast_fini(struct nouveau_object *object, bool suspend)
|
||||
}
|
||||
|
||||
struct nv50_disp_chan_impl
|
||||
nvd0_disp_mast_ofuncs = {
|
||||
.base.ctor = nv50_disp_mast_ctor,
|
||||
nvd0_disp_core_ofuncs = {
|
||||
.base.ctor = nv50_disp_core_ctor,
|
||||
.base.dtor = nv50_disp_dmac_dtor,
|
||||
.base.init = nvd0_disp_mast_init,
|
||||
.base.fini = nvd0_disp_mast_fini,
|
||||
.base.init = nvd0_disp_core_init,
|
||||
.base.fini = nvd0_disp_core_fini,
|
||||
.base.ntfy = nv50_disp_chan_ntfy,
|
||||
.base.map = nv50_disp_chan_map,
|
||||
.base.rd32 = nv50_disp_chan_rd32,
|
||||
@ -363,7 +363,7 @@ nvd0_disp_mast_ofuncs = {
|
||||
******************************************************************************/
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
nvd0_disp_sync_mthd_base = {
|
||||
nvd0_disp_base_mthd_base = {
|
||||
.mthd = 0x0000,
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
@ -413,7 +413,7 @@ nvd0_disp_sync_mthd_base = {
|
||||
};
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
nvd0_disp_sync_mthd_image = {
|
||||
nvd0_disp_base_mthd_image = {
|
||||
.mthd = 0x0400,
|
||||
.addr = 0x000400,
|
||||
.data = {
|
||||
@ -427,19 +427,19 @@ nvd0_disp_sync_mthd_image = {
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
nvd0_disp_sync_mthd_chan = {
|
||||
nvd0_disp_base_mthd_chan = {
|
||||
.name = "Base",
|
||||
.addr = 0x001000,
|
||||
.data = {
|
||||
{ "Global", 1, &nvd0_disp_sync_mthd_base },
|
||||
{ "Image", 2, &nvd0_disp_sync_mthd_image },
|
||||
{ "Global", 1, &nvd0_disp_base_mthd_base },
|
||||
{ "Image", 2, &nvd0_disp_base_mthd_image },
|
||||
{}
|
||||
}
|
||||
};
|
||||
|
||||
struct nv50_disp_chan_impl
|
||||
nvd0_disp_sync_ofuncs = {
|
||||
.base.ctor = nv50_disp_sync_ctor,
|
||||
nvd0_disp_base_ofuncs = {
|
||||
.base.ctor = nv50_disp_base_ctor,
|
||||
.base.dtor = nv50_disp_dmac_dtor,
|
||||
.base.init = nvd0_disp_dmac_init,
|
||||
.base.fini = nvd0_disp_dmac_fini,
|
||||
@ -624,7 +624,7 @@ nvd0_disp_curs_ofuncs = {
|
||||
******************************************************************************/
|
||||
|
||||
int
|
||||
nvd0_disp_base_scanoutpos(NV50_DISP_MTHD_V0)
|
||||
nvd0_disp_main_scanoutpos(NV50_DISP_MTHD_V0)
|
||||
{
|
||||
const u32 total = nv_rd32(priv, 0x640414 + (head * 0x300));
|
||||
const u32 blanke = nv_rd32(priv, 0x64041c + (head * 0x300));
|
||||
@ -656,7 +656,7 @@ nvd0_disp_base_scanoutpos(NV50_DISP_MTHD_V0)
|
||||
}
|
||||
|
||||
static int
|
||||
nvd0_disp_base_init(struct nouveau_object *object)
|
||||
nvd0_disp_main_init(struct nouveau_object *object)
|
||||
{
|
||||
struct nv50_disp_priv *priv = (void *)object->engine;
|
||||
struct nv50_disp_base *base = (void *)object;
|
||||
@ -725,7 +725,7 @@ nvd0_disp_base_init(struct nouveau_object *object)
|
||||
}
|
||||
|
||||
static int
|
||||
nvd0_disp_base_fini(struct nouveau_object *object, bool suspend)
|
||||
nvd0_disp_main_fini(struct nouveau_object *object, bool suspend)
|
||||
{
|
||||
struct nv50_disp_priv *priv = (void *)object->engine;
|
||||
struct nv50_disp_base *base = (void *)object;
|
||||
@ -737,25 +737,25 @@ nvd0_disp_base_fini(struct nouveau_object *object, bool suspend)
|
||||
}
|
||||
|
||||
struct nouveau_ofuncs
|
||||
nvd0_disp_base_ofuncs = {
|
||||
.ctor = nv50_disp_base_ctor,
|
||||
.dtor = nv50_disp_base_dtor,
|
||||
.init = nvd0_disp_base_init,
|
||||
.fini = nvd0_disp_base_fini,
|
||||
.mthd = nv50_disp_base_mthd,
|
||||
nvd0_disp_main_ofuncs = {
|
||||
.ctor = nv50_disp_main_ctor,
|
||||
.dtor = nv50_disp_main_dtor,
|
||||
.init = nvd0_disp_main_init,
|
||||
.fini = nvd0_disp_main_fini,
|
||||
.mthd = nv50_disp_main_mthd,
|
||||
.ntfy = nouveau_disp_ntfy,
|
||||
};
|
||||
|
||||
static struct nouveau_oclass
|
||||
nvd0_disp_base_oclass[] = {
|
||||
{ GF110_DISP, &nvd0_disp_base_ofuncs },
|
||||
nvd0_disp_main_oclass[] = {
|
||||
{ GF110_DISP, &nvd0_disp_main_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
static struct nouveau_oclass
|
||||
nvd0_disp_sclass[] = {
|
||||
{ GF110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
|
||||
{ GF110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
|
||||
{ GF110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
|
||||
{ GF110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
|
||||
{ GF110_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
|
||||
{ GF110_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
|
||||
{ GF110_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
|
||||
@ -1270,7 +1270,7 @@ nvd0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(priv)->sclass = nvd0_disp_base_oclass;
|
||||
nv_engine(priv)->sclass = nvd0_disp_main_oclass;
|
||||
nv_engine(priv)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(priv)->intr = nvd0_disp_intr;
|
||||
INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
|
||||
@ -1303,9 +1303,9 @@ nvd0_disp_oclass = &(struct nv50_disp_impl) {
|
||||
},
|
||||
.base.vblank = &nvd0_disp_vblank_func,
|
||||
.base.outp = nvd0_disp_outp_sclass,
|
||||
.mthd.core = &nvd0_disp_mast_mthd_chan,
|
||||
.mthd.base = &nvd0_disp_sync_mthd_chan,
|
||||
.mthd.core = &nvd0_disp_core_mthd_chan,
|
||||
.mthd.base = &nvd0_disp_base_mthd_chan,
|
||||
.mthd.ovly = &nvd0_disp_ovly_mthd_chan,
|
||||
.mthd.prev = -0x020000,
|
||||
.head.scanoutpos = nvd0_disp_base_scanoutpos,
|
||||
.head.scanoutpos = nvd0_disp_main_scanoutpos,
|
||||
}.base.base;
|
||||
|
||||
@ -34,7 +34,7 @@
|
||||
******************************************************************************/
|
||||
|
||||
static const struct nv50_disp_mthd_list
|
||||
nve0_disp_mast_mthd_head = {
|
||||
nve0_disp_core_mthd_head = {
|
||||
.mthd = 0x0300,
|
||||
.addr = 0x000300,
|
||||
.data = {
|
||||
@ -113,15 +113,15 @@ nve0_disp_mast_mthd_head = {
|
||||
};
|
||||
|
||||
const struct nv50_disp_mthd_chan
|
||||
nve0_disp_mast_mthd_chan = {
|
||||
nve0_disp_core_mthd_chan = {
|
||||
.name = "Core",
|
||||
.addr = 0x000000,
|
||||
.data = {
|
||||
{ "Global", 1, &nvd0_disp_mast_mthd_base },
|
||||
{ "DAC", 3, &nvd0_disp_mast_mthd_dac },
|
||||
{ "SOR", 8, &nvd0_disp_mast_mthd_sor },
|
||||
{ "PIOR", 4, &nvd0_disp_mast_mthd_pior },
|
||||
{ "HEAD", 4, &nve0_disp_mast_mthd_head },
|
||||
{ "Global", 1, &nvd0_disp_core_mthd_base },
|
||||
{ "DAC", 3, &nvd0_disp_core_mthd_dac },
|
||||
{ "SOR", 8, &nvd0_disp_core_mthd_sor },
|
||||
{ "PIOR", 4, &nvd0_disp_core_mthd_pior },
|
||||
{ "HEAD", 4, &nve0_disp_core_mthd_head },
|
||||
{}
|
||||
}
|
||||
};
|
||||
@ -200,8 +200,8 @@ nve0_disp_ovly_mthd_chan = {
|
||||
|
||||
static struct nouveau_oclass
|
||||
nve0_disp_sclass[] = {
|
||||
{ GK104_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
|
||||
{ GK104_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
|
||||
{ GK104_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
|
||||
{ GK104_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
|
||||
{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
|
||||
@ -209,8 +209,8 @@ nve0_disp_sclass[] = {
|
||||
};
|
||||
|
||||
static struct nouveau_oclass
|
||||
nve0_disp_base_oclass[] = {
|
||||
{ GK104_DISP, &nvd0_disp_base_ofuncs },
|
||||
nve0_disp_main_oclass[] = {
|
||||
{ GK104_DISP, &nvd0_disp_main_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
@ -237,7 +237,7 @@ nve0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(priv)->sclass = nve0_disp_base_oclass;
|
||||
nv_engine(priv)->sclass = nve0_disp_main_oclass;
|
||||
nv_engine(priv)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(priv)->intr = nvd0_disp_intr;
|
||||
INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
|
||||
@ -264,9 +264,9 @@ nve0_disp_oclass = &(struct nv50_disp_impl) {
|
||||
},
|
||||
.base.vblank = &nvd0_disp_vblank_func,
|
||||
.base.outp = nvd0_disp_outp_sclass,
|
||||
.mthd.core = &nve0_disp_mast_mthd_chan,
|
||||
.mthd.base = &nvd0_disp_sync_mthd_chan,
|
||||
.mthd.core = &nve0_disp_core_mthd_chan,
|
||||
.mthd.base = &nvd0_disp_base_mthd_chan,
|
||||
.mthd.ovly = &nve0_disp_ovly_mthd_chan,
|
||||
.mthd.prev = -0x020000,
|
||||
.head.scanoutpos = nvd0_disp_base_scanoutpos,
|
||||
.head.scanoutpos = nvd0_disp_main_scanoutpos,
|
||||
}.base.base;
|
||||
|
||||
@ -35,8 +35,8 @@
|
||||
|
||||
static struct nouveau_oclass
|
||||
nvf0_disp_sclass[] = {
|
||||
{ GK110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_mast_ofuncs.base },
|
||||
{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_sync_ofuncs.base },
|
||||
{ GK110_DISP_CORE_CHANNEL_DMA, &nvd0_disp_core_ofuncs.base },
|
||||
{ GK110_DISP_BASE_CHANNEL_DMA, &nvd0_disp_base_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY_CONTROL_DMA, &nvd0_disp_ovly_ofuncs.base },
|
||||
{ GK104_DISP_OVERLAY, &nvd0_disp_oimm_ofuncs.base },
|
||||
{ GK104_DISP_CURSOR, &nvd0_disp_curs_ofuncs.base },
|
||||
@ -44,8 +44,8 @@ nvf0_disp_sclass[] = {
|
||||
};
|
||||
|
||||
static struct nouveau_oclass
|
||||
nvf0_disp_base_oclass[] = {
|
||||
{ GK110_DISP, &nvd0_disp_base_ofuncs },
|
||||
nvf0_disp_main_oclass[] = {
|
||||
{ GK110_DISP, &nvd0_disp_main_ofuncs },
|
||||
{}
|
||||
};
|
||||
|
||||
@ -72,7 +72,7 @@ nvf0_disp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
nv_engine(priv)->sclass = nvf0_disp_base_oclass;
|
||||
nv_engine(priv)->sclass = nvf0_disp_main_oclass;
|
||||
nv_engine(priv)->cclass = &nv50_disp_cclass;
|
||||
nv_subdev(priv)->intr = nvd0_disp_intr;
|
||||
INIT_WORK(&priv->supervisor, nvd0_disp_intr_supervisor);
|
||||
@ -99,9 +99,9 @@ nvf0_disp_oclass = &(struct nv50_disp_impl) {
|
||||
},
|
||||
.base.vblank = &nvd0_disp_vblank_func,
|
||||
.base.outp = nvd0_disp_outp_sclass,
|
||||
.mthd.core = &nve0_disp_mast_mthd_chan,
|
||||
.mthd.base = &nvd0_disp_sync_mthd_chan,
|
||||
.mthd.core = &nve0_disp_core_mthd_chan,
|
||||
.mthd.base = &nvd0_disp_base_mthd_chan,
|
||||
.mthd.ovly = &nve0_disp_ovly_mthd_chan,
|
||||
.mthd.prev = -0x020000,
|
||||
.head.scanoutpos = nvd0_disp_base_scanoutpos,
|
||||
.head.scanoutpos = nvd0_disp_main_scanoutpos,
|
||||
}.base.base;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user