mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 10:30:52 +07:00
drm/nouveau/dp: restructure link training code
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
a002feceb7
commit
27a4598737
@ -1179,19 +1179,18 @@ init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
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*
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*/
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struct bit_displayport_encoder_table *dpe = NULL;
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struct dcb_entry *dcb = bios->display.output;
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struct drm_device *dev = bios->dev;
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uint8_t cond = bios->data[offset + 1];
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int dummy;
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uint8_t *table, headerlen;
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BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
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if (!iexec->execute)
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return 3;
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dpe = nouveau_bios_dp_table(dev, dcb, &dummy);
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if (!dpe) {
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table = nouveau_bios_dp_table(dev, dcb, &headerlen);
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if (!table) {
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NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset);
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return 3;
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}
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@ -1208,7 +1207,7 @@ init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
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break;
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case 1:
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case 2:
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if (!(dpe->unknown & cond))
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if (!(table[5] & cond))
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iexec->execute = false;
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break;
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case 5:
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@ -4480,7 +4479,7 @@ bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
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void *
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nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
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int *length)
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uint8_t *headerlen)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nvbios *bios = &dev_priv->vbios;
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@ -4498,7 +4497,7 @@ nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
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return NULL;
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}
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*length = table[4];
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*headerlen = table[4];
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return bios_output_config_match(dev, dcbent,
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bios->display.dp_table_ptr + table[1],
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table[2], table[3], table[0] >= 0x21);
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@ -28,6 +28,7 @@
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#include "nouveau_i2c.h"
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#include "nouveau_connector.h"
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#include "nouveau_encoder.h"
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#include "nouveau_crtc.h"
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/******************************************************************************
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* aux channel util functions
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@ -178,22 +179,6 @@ auxch_rd(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
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return 0;
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}
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static int
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auxch_wr(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
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{
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struct drm_device *dev = encoder->dev;
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct nouveau_i2c_chan *auxch;
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int ret;
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auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
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if (!auxch)
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return -ENODEV;
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ret = nouveau_dp_auxch(auxch, 8, address, buf, size);
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return ret;
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}
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static u32
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dp_link_bw_get(struct drm_device *dev, int or, int link)
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{
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@ -304,382 +289,269 @@ nouveau_dp_tu_update(struct drm_device *dev, int or, int link, u32 clk, u32 bpp)
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unk);
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}
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static int
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nouveau_dp_lane_count_set(struct drm_encoder *encoder, uint8_t cmd)
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/******************************************************************************
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* link training
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*****************************************************************************/
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struct dp_state {
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struct dcb_entry *dcb;
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int auxch;
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int crtc;
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int or;
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int link;
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int enh_frame;
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int link_nr;
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u32 link_bw;
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u8 stat[6];
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u8 conf[4];
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};
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static void
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dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
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{
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struct drm_device *dev = encoder->dev;
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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uint32_t tmp;
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int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
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int or = dp->or, link = dp->link;
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u32 clk_sor, dp_ctrl;
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u8 sink[2];
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tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
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tmp &= ~(NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED |
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NV50_SOR_DP_CTRL_LANE_MASK);
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tmp |= ((1 << (cmd & DP_LANE_COUNT_MASK)) - 1) << 16;
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if (cmd & DP_LANE_COUNT_ENHANCED_FRAME_EN)
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tmp |= NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED;
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nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
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NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
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return auxch_wr(encoder, DP_LANE_COUNT_SET, &cmd, 1);
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switch (dp->link_bw) {
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case 270000:
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clk_sor = 0x00040000;
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sink[0] = DP_LINK_BW_2_7;
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break;
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default:
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clk_sor = 0x00000000;
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sink[0] = DP_LINK_BW_1_62;
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break;
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}
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dp_ctrl = ((1 << dp->link_nr) - 1) << 16;
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sink[1] = dp->link_nr;
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if (dp->enh_frame) {
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dp_ctrl |= 0x00004000;
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sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
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}
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nv_mask(dev, 0x614300 + (or * 0x800), 0x000c0000, clk_sor);
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nv_mask(dev, NV50_SOR_DP_CTRL(or, link), 0x001f4000, dp_ctrl);
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auxch_tx(dev, dp->auxch, 8, DP_LINK_BW_SET, sink, 2);
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}
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static void
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dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 tp)
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{
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NV_DEBUG_KMS(dev, "training pattern %d\n", tp);
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nv_mask(dev, NV50_SOR_DP_CTRL(dp->or, dp->link), 0x0f000000, tp << 24);
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auxch_tx(dev, dp->auxch, 8, DP_TRAINING_PATTERN_SET, &tp, 1);
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}
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static int
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nouveau_dp_link_bw_set(struct drm_encoder *encoder, uint8_t cmd)
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dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
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{
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struct drm_device *dev = encoder->dev;
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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uint32_t tmp;
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int reg = 0x614300 + (nv_encoder->or * 0x800);
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u32 mask = 0, drv = 0, pre = 0, unk = 0;
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u8 shifts[4] = { 16, 8, 0, 24 };
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u8 *bios, *last, headerlen;
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int link = dp->link;
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int or = dp->or;
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int i;
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tmp = nv_rd32(dev, reg);
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tmp &= 0xfff3ffff;
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if (cmd == DP_LINK_BW_2_7)
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tmp |= 0x00040000;
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nv_wr32(dev, reg, tmp);
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bios = nouveau_bios_dp_table(dev, dp->dcb, &headerlen);
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last = bios + headerlen + (bios[4] * 5);
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for (i = 0; i < dp->link_nr; i++) {
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u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
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u8 *conf = bios + headerlen;
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return auxch_wr(encoder, DP_LINK_BW_SET, &cmd, 1);
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while (conf < last) {
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if ((lane & 3) == conf[0] &&
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(lane >> 2) == conf[1])
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break;
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conf += 5;
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}
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if (conf == last)
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return -EINVAL;
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dp->conf[i] = (conf[1] << 3) | conf[0];
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if (conf[0] == DP_TRAIN_VOLTAGE_SWING_1200)
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dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
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if (conf[1] == DP_TRAIN_PRE_EMPHASIS_9_5)
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dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
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NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);
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mask |= 0xff << shifts[i];
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drv |= conf[2] << shifts[i];
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pre |= conf[3] << shifts[i];
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unk = (unk & ~0x0000ff00) | (conf[4] << 8);
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unk |= 1 << (shifts[i] >> 3);
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}
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nv_mask(dev, NV50_SOR_DP_UNK118(or, link), mask, drv);
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nv_mask(dev, NV50_SOR_DP_UNK120(or, link), mask, pre);
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nv_mask(dev, NV50_SOR_DP_UNK130(or, link), 0x0000ff0f, unk);
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return auxch_tx(dev, dp->auxch, 8, DP_TRAINING_LANE0_SET, dp->conf, 4);
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}
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static int
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nouveau_dp_link_train_set(struct drm_encoder *encoder, int pattern)
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dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
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{
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struct drm_device *dev = encoder->dev;
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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uint32_t tmp;
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uint8_t cmd;
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int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
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int ret;
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tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
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tmp &= ~NV50_SOR_DP_CTRL_TRAINING_PATTERN;
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tmp |= (pattern << 24);
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nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
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udelay(delay);
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ret = auxch_rd(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
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ret = auxch_tx(dev, dp->auxch, 9, DP_LANE0_1_STATUS, dp->stat, 6);
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if (ret)
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return ret;
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cmd &= ~DP_TRAINING_PATTERN_MASK;
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cmd |= (pattern & DP_TRAINING_PATTERN_MASK);
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return auxch_wr(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
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NV_DEBUG_KMS(dev, "status %02x %02x %02x %02x %02x %02x\n",
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dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3],
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dp->stat[4], dp->stat[5]);
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return 0;
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}
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static int
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nouveau_dp_max_voltage_swing(struct drm_encoder *encoder)
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dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct drm_device *dev = encoder->dev;
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struct bit_displayport_encoder_table_entry *dpse;
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struct bit_displayport_encoder_table *dpe;
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int i, dpe_headerlen, max_vs = 0;
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bool cr_done = false, abort = false;
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int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
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int tries = 0, i;
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dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
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if (!dpe)
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return false;
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dpse = (void *)((char *)dpe + dpe_headerlen);
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dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
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for (i = 0; i < dpe_headerlen; i++, dpse++) {
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if (dpse->vs_level > max_vs)
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max_vs = dpse->vs_level;
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}
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return max_vs;
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}
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static int
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nouveau_dp_max_pre_emphasis(struct drm_encoder *encoder, int vs)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct drm_device *dev = encoder->dev;
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struct bit_displayport_encoder_table_entry *dpse;
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struct bit_displayport_encoder_table *dpe;
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int i, dpe_headerlen, max_pre = 0;
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dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
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if (!dpe)
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return false;
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dpse = (void *)((char *)dpe + dpe_headerlen);
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for (i = 0; i < dpe_headerlen; i++, dpse++) {
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if (dpse->vs_level != vs)
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continue;
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if (dpse->pre_level > max_pre)
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max_pre = dpse->pre_level;
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}
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return max_pre;
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}
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static bool
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nouveau_dp_link_train_adjust(struct drm_encoder *encoder, uint8_t *config)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct drm_device *dev = encoder->dev;
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struct bit_displayport_encoder_table *dpe;
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int ret, i, dpe_headerlen, vs = 0, pre = 0;
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uint8_t request[2];
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dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
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if (!dpe)
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return false;
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ret = auxch_rd(encoder, DP_ADJUST_REQUEST_LANE0_1, request, 2);
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if (ret)
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return false;
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NV_DEBUG_KMS(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]);
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/* Keep all lanes at the same level.. */
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for (i = 0; i < nv_encoder->dp.link_nr; i++) {
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int lane_req = (request[i >> 1] >> ((i & 1) << 2)) & 0xf;
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int lane_vs = lane_req & 3;
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int lane_pre = (lane_req >> 2) & 3;
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if (lane_vs > vs)
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vs = lane_vs;
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if (lane_pre > pre)
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pre = lane_pre;
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}
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if (vs >= nouveau_dp_max_voltage_swing(encoder)) {
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vs = nouveau_dp_max_voltage_swing(encoder);
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vs |= 4;
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}
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if (pre >= nouveau_dp_max_pre_emphasis(encoder, vs & 3)) {
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pre = nouveau_dp_max_pre_emphasis(encoder, vs & 3);
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pre |= 4;
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}
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/* Update the configuration for all lanes.. */
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for (i = 0; i < nv_encoder->dp.link_nr; i++)
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config[i] = (pre << 3) | vs;
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return true;
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}
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static bool
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nouveau_dp_link_train_commit(struct drm_encoder *encoder, uint8_t *config)
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{
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struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
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struct drm_device *dev = encoder->dev;
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struct bit_displayport_encoder_table_entry *dpse;
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struct bit_displayport_encoder_table *dpe;
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int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
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int dpe_headerlen, ret, i;
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NV_DEBUG_KMS(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n",
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config[0], config[1], config[2], config[3]);
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dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
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if (!dpe)
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return false;
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dpse = (void *)((char *)dpe + dpe_headerlen);
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for (i = 0; i < dpe->record_nr; i++, dpse++) {
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if (dpse->vs_level == (config[0] & 3) &&
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dpse->pre_level == ((config[0] >> 3) & 3))
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do {
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if (dp_link_train_commit(dev, dp) ||
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dp_link_train_update(dev, dp, 100))
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break;
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}
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BUG_ON(i == dpe->record_nr);
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for (i = 0; i < nv_encoder->dp.link_nr; i++) {
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const int shift[4] = { 16, 8, 0, 24 };
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uint32_t mask = 0xff << shift[i];
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uint32_t reg0, reg1, reg2;
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cr_done = true;
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for (i = 0; i < dp->link_nr; i++) {
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u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
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if (!(lane & DP_LANE_CR_DONE)) {
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cr_done = false;
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if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
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abort = true;
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break;
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}
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}
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reg0 = nv_rd32(dev, NV50_SOR_DP_UNK118(or, link)) & ~mask;
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reg0 |= (dpse->reg0 << shift[i]);
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reg1 = nv_rd32(dev, NV50_SOR_DP_UNK120(or, link)) & ~mask;
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reg1 |= (dpse->reg1 << shift[i]);
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reg2 = nv_rd32(dev, NV50_SOR_DP_UNK130(or, link)) & 0xffff00ff;
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reg2 |= (dpse->reg2 << 8);
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nv_wr32(dev, NV50_SOR_DP_UNK118(or, link), reg0);
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nv_wr32(dev, NV50_SOR_DP_UNK120(or, link), reg1);
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nv_wr32(dev, NV50_SOR_DP_UNK130(or, link), reg2);
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}
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if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
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voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
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tries = 0;
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}
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} while (!cr_done && !abort && ++tries < 5);
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ret = auxch_wr(encoder, DP_TRAINING_LANE0_SET, config, 4);
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if (ret)
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return false;
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return cr_done ? 0 : -1;
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}
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return true;
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static int
|
||||
dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
|
||||
{
|
||||
bool eq_done, cr_done = true;
|
||||
int tries = 0, i;
|
||||
|
||||
dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
|
||||
|
||||
do {
|
||||
if (dp_link_train_update(dev, dp, 400))
|
||||
break;
|
||||
|
||||
eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
|
||||
for (i = 0; i < dp->link_nr && eq_done; i++) {
|
||||
u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
|
||||
if (!(lane & DP_LANE_CR_DONE))
|
||||
cr_done = false;
|
||||
if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
|
||||
!(lane & DP_LANE_SYMBOL_LOCKED))
|
||||
eq_done = false;
|
||||
}
|
||||
|
||||
if (dp_link_train_commit(dev, dp))
|
||||
break;
|
||||
} while (!eq_done && cr_done && ++tries <= 5);
|
||||
|
||||
return eq_done ? 0 : -1;
|
||||
}
|
||||
|
||||
bool
|
||||
nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate)
|
||||
{
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct drm_nouveau_private *dev_priv = encoder->dev->dev_private;
|
||||
struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
|
||||
struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
|
||||
struct nouveau_connector *nv_connector;
|
||||
struct bit_displayport_encoder_table *dpe;
|
||||
int dpe_headerlen;
|
||||
uint8_t config[4], status[3];
|
||||
bool cr_done, cr_max_vs, eq_done, hpd_state;
|
||||
int ret = 0, i, tries, voltage;
|
||||
struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
|
||||
struct nouveau_connector *nv_connector =
|
||||
nouveau_encoder_connector_get(nv_encoder);
|
||||
struct drm_device *dev = encoder->dev;
|
||||
struct nouveau_i2c_chan *auxch;
|
||||
const u32 bw_list[] = { 270000, 162000, 0 };
|
||||
const u32 *link_bw = bw_list;
|
||||
struct dp_state dp;
|
||||
u8 *bios, headerlen;
|
||||
u16 script;
|
||||
|
||||
NV_DEBUG_KMS(dev, "link training!!\n");
|
||||
|
||||
nv_connector = nouveau_encoder_connector_get(nv_encoder);
|
||||
if (!nv_connector)
|
||||
auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
|
||||
if (!auxch)
|
||||
return false;
|
||||
|
||||
dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
|
||||
if (!dpe) {
|
||||
NV_ERROR(dev, "SOR-%d: no DP encoder table!\n", nv_encoder->or);
|
||||
return false;
|
||||
}
|
||||
bios = nouveau_bios_dp_table(dev, nv_encoder->dcb, &headerlen);
|
||||
if (!bios)
|
||||
return -EINVAL;
|
||||
|
||||
/* disable hotplug detect, this flips around on some panels during
|
||||
* link training.
|
||||
dp.dcb = nv_encoder->dcb;
|
||||
dp.crtc = nv_crtc->index;
|
||||
dp.auxch = auxch->rd;
|
||||
dp.or = nv_encoder->or;
|
||||
dp.link = !(nv_encoder->dcb->sorconf.link & 1);
|
||||
dp.enh_frame = nv_encoder->dp.enhanced_frame;
|
||||
|
||||
/* some sinks toggle hotplug in response to some of the actions
|
||||
* we take during link training (DP_SET_POWER is one), we need
|
||||
* to ignore them for the moment to avoid races.
|
||||
*/
|
||||
hpd_state = pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, false);
|
||||
pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, false);
|
||||
|
||||
if (dpe->script0) {
|
||||
NV_DEBUG_KMS(dev, "SOR-%d: running DP script 0\n", nv_encoder->or);
|
||||
nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script0),
|
||||
nv_encoder->dcb, -1);
|
||||
/* execute pre-train script from vbios */
|
||||
nouveau_bios_run_init_table(dev, ROM16(bios[6]), dp.dcb, dp.crtc);
|
||||
|
||||
/* start off at highest link rate supported by encoder and display */
|
||||
if (nv_encoder->dp.link_bw == DP_LINK_BW_1_62)
|
||||
link_bw++;
|
||||
|
||||
while (link_bw[0]) {
|
||||
/* find minimum required lane count at this link rate */
|
||||
dp.link_nr = nv_encoder->dp.link_nr;
|
||||
while ((dp.link_nr >> 1) * link_bw[0] > datarate)
|
||||
dp.link_nr >>= 1;
|
||||
|
||||
/* drop link rate to minimum with this lane count */
|
||||
while ((link_bw[1] * dp.link_nr) > datarate)
|
||||
link_bw++;
|
||||
dp.link_bw = link_bw[0];
|
||||
|
||||
/* program selected link configuration */
|
||||
dp_set_link_config(dev, &dp);
|
||||
|
||||
/* attempt to train the link at this configuration */
|
||||
memset(dp.stat, 0x00, sizeof(dp.stat));
|
||||
if (!dp_link_train_cr(dev, &dp) &&
|
||||
!dp_link_train_eq(dev, &dp))
|
||||
break;
|
||||
|
||||
/* retry at lower rate */
|
||||
link_bw++;
|
||||
}
|
||||
|
||||
train:
|
||||
cr_done = eq_done = false;
|
||||
/* finish link training */
|
||||
dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
|
||||
|
||||
/* set link configuration */
|
||||
NV_DEBUG_KMS(dev, "\tbegin train: bw %d, lanes %d\n",
|
||||
nv_encoder->dp.link_bw, nv_encoder->dp.link_nr);
|
||||
|
||||
ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw);
|
||||
if (ret)
|
||||
return false;
|
||||
|
||||
config[0] = nv_encoder->dp.link_nr;
|
||||
if (nv_encoder->dp.dpcd_version >= 0x11 &&
|
||||
nv_encoder->dp.enhanced_frame)
|
||||
config[0] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
|
||||
|
||||
ret = nouveau_dp_lane_count_set(encoder, config[0]);
|
||||
if (ret)
|
||||
return false;
|
||||
|
||||
/* clock recovery */
|
||||
NV_DEBUG_KMS(dev, "\tbegin cr\n");
|
||||
ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1);
|
||||
if (ret)
|
||||
goto stop;
|
||||
|
||||
tries = 0;
|
||||
voltage = -1;
|
||||
memset(config, 0x00, sizeof(config));
|
||||
for (;;) {
|
||||
if (!nouveau_dp_link_train_commit(encoder, config))
|
||||
break;
|
||||
|
||||
udelay(100);
|
||||
|
||||
ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2);
|
||||
if (ret)
|
||||
break;
|
||||
NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
|
||||
status[0], status[1]);
|
||||
|
||||
cr_done = true;
|
||||
cr_max_vs = false;
|
||||
for (i = 0; i < nv_encoder->dp.link_nr; i++) {
|
||||
int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
|
||||
|
||||
if (!(lane & DP_LANE_CR_DONE)) {
|
||||
cr_done = false;
|
||||
if (config[i] & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED)
|
||||
cr_max_vs = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if ((config[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
|
||||
voltage = config[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
|
||||
tries = 0;
|
||||
}
|
||||
|
||||
if (cr_done || cr_max_vs || (++tries == 5))
|
||||
break;
|
||||
|
||||
if (!nouveau_dp_link_train_adjust(encoder, config))
|
||||
break;
|
||||
}
|
||||
|
||||
if (!cr_done)
|
||||
goto stop;
|
||||
|
||||
/* channel equalisation */
|
||||
NV_DEBUG_KMS(dev, "\tbegin eq\n");
|
||||
ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2);
|
||||
if (ret)
|
||||
goto stop;
|
||||
|
||||
for (tries = 0; tries <= 5; tries++) {
|
||||
udelay(400);
|
||||
|
||||
ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3);
|
||||
if (ret)
|
||||
break;
|
||||
NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
|
||||
status[0], status[1]);
|
||||
|
||||
eq_done = true;
|
||||
if (!(status[2] & DP_INTERLANE_ALIGN_DONE))
|
||||
eq_done = false;
|
||||
|
||||
for (i = 0; eq_done && i < nv_encoder->dp.link_nr; i++) {
|
||||
int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
|
||||
|
||||
if (!(lane & DP_LANE_CR_DONE)) {
|
||||
cr_done = false;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
|
||||
!(lane & DP_LANE_SYMBOL_LOCKED)) {
|
||||
eq_done = false;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (eq_done || !cr_done)
|
||||
break;
|
||||
|
||||
if (!nouveau_dp_link_train_adjust(encoder, config) ||
|
||||
!nouveau_dp_link_train_commit(encoder, config))
|
||||
break;
|
||||
}
|
||||
|
||||
stop:
|
||||
/* end link training */
|
||||
ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_DISABLE);
|
||||
if (ret)
|
||||
return false;
|
||||
|
||||
/* retry at a lower setting, if possible */
|
||||
if (!ret && !(eq_done && cr_done)) {
|
||||
NV_DEBUG_KMS(dev, "\twe failed\n");
|
||||
if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) {
|
||||
NV_DEBUG_KMS(dev, "retry link training at low rate\n");
|
||||
nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
|
||||
goto train;
|
||||
}
|
||||
}
|
||||
|
||||
if (dpe->script1) {
|
||||
NV_DEBUG_KMS(dev, "SOR-%d: running DP script 1\n", nv_encoder->or);
|
||||
nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script1),
|
||||
nv_encoder->dcb, -1);
|
||||
}
|
||||
/* execute post-train script from vbios */
|
||||
nouveau_bios_run_init_table(dev, ROM16(bios[8]), dp.dcb, dp.crtc);
|
||||
|
||||
/* re-enable hotplug detect */
|
||||
pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, hpd_state);
|
||||
|
||||
return eq_done;
|
||||
pgpio->irq_enable(dev, nv_connector->dcb->gpio_tag, true);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool
|
||||
|
||||
@ -1081,7 +1081,7 @@ extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
|
||||
extern int nouveau_bios_run_display_table(struct drm_device *, u16 id, int clk,
|
||||
struct dcb_entry *, int crtc);
|
||||
extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
|
||||
int *length);
|
||||
u8 *headerlen);
|
||||
extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
|
||||
extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
|
||||
extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
|
||||
|
||||
@ -84,21 +84,4 @@ nouveau_encoder_connector_get(struct nouveau_encoder *encoder);
|
||||
int nv50_sor_create(struct drm_connector *, struct dcb_entry *);
|
||||
int nv50_dac_create(struct drm_connector *, struct dcb_entry *);
|
||||
|
||||
struct bit_displayport_encoder_table {
|
||||
uint32_t match;
|
||||
uint8_t record_nr;
|
||||
uint8_t unknown;
|
||||
uint16_t script0;
|
||||
uint16_t script1;
|
||||
uint16_t unknown_table;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct bit_displayport_encoder_table_entry {
|
||||
uint8_t vs_level;
|
||||
uint8_t pre_level;
|
||||
uint8_t reg0;
|
||||
uint8_t reg1;
|
||||
uint8_t reg2;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#endif /* __NOUVEAU_ENCODER_H__ */
|
||||
|
||||
Loading…
Reference in New Issue
Block a user