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drm/amd/pm: perform SMC reset on suspend/hibernation

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So that the succeeding resume can be performed based on
a clean state.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Tested-by: Sandeep Raghuraman <sandy.8925@gmail.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2020-10-16 10:45:26 +08:00 committed by Alex Deucher
parent 2a4776a733
commit 277b080f98
5 changed files with 39 additions and 0 deletions
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1
drivers/gpu/drm/amd/pm/inc/hwmgr.h
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@ -229,6 +229,7 @@ struct pp_smumgr_func {
bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr); bool (*is_hw_avfs_present)(struct pp_hwmgr *hwmgr);
int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting); int (*update_dpm_settings)(struct pp_hwmgr *hwmgr, void *profile_setting);
int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */ int (*smc_table_manager)(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); /*rw: true for read, false for write */
int (*stop_smc)(struct pp_hwmgr *hwmgr);
}; };
struct pp_hwmgr_func { struct pp_hwmgr_func {

2
drivers/gpu/drm/amd/pm/inc/smumgr.h
View File

@ -113,4 +113,6 @@ extern int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_settin
extern int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); extern int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw);
extern int smum_stop_smc(struct pp_hwmgr *hwmgr);
#endif #endif

4
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
View File

@ -1541,6 +1541,10 @@ static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to reset to default!", result = tmp_result); "Failed to reset to default!", result = tmp_result);
tmp_result = smum_stop_smc(hwmgr);
PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to stop smc!", result = tmp_result);
tmp_result = smu7_force_switch_to_arbf0(hwmgr); tmp_result = smu7_force_switch_to_arbf0(hwmgr);
PP_ASSERT_WITH_CODE((tmp_result == 0), PP_ASSERT_WITH_CODE((tmp_result == 0),
"Failed to force to switch arbf0!", result = tmp_result); "Failed to force to switch arbf0!", result = tmp_result);

24
drivers/gpu/drm/amd/pm/powerplay/smumgr/ci_smumgr.c
View File

@ -2939,6 +2939,29 @@ static int ci_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
return 0; return 0;
} }
static void ci_reset_smc(struct pp_hwmgr *hwmgr)
{
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_RESET_CNTL,
rst_reg, 1);
}
static void ci_stop_smc_clock(struct pp_hwmgr *hwmgr)
{
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
SMC_SYSCON_CLOCK_CNTL_0,
ck_disable, 1);
}
static int ci_stop_smc(struct pp_hwmgr *hwmgr)
{
ci_reset_smc(hwmgr);
ci_stop_smc_clock(hwmgr);
return 0;
}
const struct pp_smumgr_func ci_smu_funcs = { const struct pp_smumgr_func ci_smu_funcs = {
.name = "ci_smu", .name = "ci_smu",
.smu_init = ci_smu_init, .smu_init = ci_smu_init,
@ -2964,4 +2987,5 @@ const struct pp_smumgr_func ci_smu_funcs = {
.is_dpm_running = ci_is_dpm_running, .is_dpm_running = ci_is_dpm_running,
.update_dpm_settings = ci_update_dpm_settings, .update_dpm_settings = ci_update_dpm_settings,
.update_smc_table = ci_update_smc_table, .update_smc_table = ci_update_smc_table,
.stop_smc = ci_stop_smc,
}; };

8
drivers/gpu/drm/amd/pm/powerplay/smumgr/smumgr.c
View File

@ -245,3 +245,11 @@ int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t tabl
return -EINVAL; return -EINVAL;
} }
int smum_stop_smc(struct pp_hwmgr *hwmgr)
{
if (hwmgr->smumgr_funcs->stop_smc)
return hwmgr->smumgr_funcs->stop_smc(hwmgr);
return 0;
}