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ARM: tegra: Add device-tree for ASUS Google Nexus 7

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There are few hardware variants of NVIDIA Tegra30-based Nexus 7 device:

1. WiFi-only (named Grouper)
2. GSM (named Tilapia)
3. Using Maxim PMIC (E1565 board ID)
4. Using Ti PMIC (PM269 board ID)

This patch adds device-trees for known and tested variants.

Link: https://wiki.postmarketos.org/wiki/Google_Nexus_7_2012_(asus-grouper)
Tested-by: Pedro Ângelo <pangelo@void.io>
Tested-by: Matt Merhar <mattmerhar@protonmail.com>
Tested-by: Zack Pearsall <zpearsall@yahoo.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This commit is contained in:
Dmitry Osipenko 2020-06-29 05:54:52 +03:00 committed by Thierry Reding
parent 674b5102e3
commit 2720008f42
11 changed files with 3870 additions and 0 deletions
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3
arch/arm/boot/dts/Makefile
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@ -1211,6 +1211,9 @@ dtb-$(CONFIG_ARCH_TEGRA_2x_SOC) += \
dtb-$(CONFIG_ARCH_TEGRA_3x_SOC) += \
tegra30-apalis-eval.dtb \
tegra30-apalis-v1.1-eval.dtb \
tegra30-asus-nexus7-grouper-PM269.dtb \
tegra30-asus-nexus7-grouper-E1565.dtb \
tegra30-asus-nexus7-tilapia-E1565.dtb \
tegra30-beaver.dtb \
tegra30-cardhu-a02.dtb \
tegra30-cardhu-a04.dtb \

9
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-E1565.dts Normal file
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@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-asus-nexus7-grouper-maxim-pmic.dtsi"
#include "tegra30-asus-nexus7-grouper.dtsi"
/ {
model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) E1565";
};

9
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-PM269.dts Normal file
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@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-asus-nexus7-grouper-ti-pmic.dtsi"
#include "tegra30-asus-nexus7-grouper.dtsi"
/ {
model = "ASUS Google Nexus 7 (Project Nakasi / ME370T) PM269";
};

1232
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi Normal file
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185
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi Normal file
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@ -0,0 +1,185 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mfd/max77620.h>
/ {
i2c@7000d000 {
pmic: pmic@3c {
compatible = "maxim,max77663";
reg = <0x3c>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
#gpio-cells = <2>;
gpio-controller;
system-power-controller;
pinctrl-names = "default";
pinctrl-0 = <&max77620_default>;
max77620_default: pinmux {
gpio4 {
pins = "gpio4";
function = "32k-out1";
};
};
cpu-pwr-req {
gpio-hog;
gpios = <6 GPIO_ACTIVE_HIGH>;
input;
};
fps {
fps0 {
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
};
fps1 {
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>;
};
fps2 {
maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>;
};
};
regulators {
in-sd0-supply = <&vdd_5v0_sys>;
in-sd1-supply = <&vdd_5v0_sys>;
in-sd2-supply = <&vdd_5v0_sys>;
in-sd3-supply = <&vdd_5v0_sys>;
in-sd4-supply = <&vdd_5v0_sys>;
in-ldo0-1-supply = <&vdd_1v35>;
in-ldo2-supply = <&vdd_3v3_sys>;
in-ldo3-5-supply = <&vdd_3v3_sys>;
in-ldo4-6-supply = <&vdd_5v0_sys>;
in-ldo7-8-supply = <&vdd_1v35>;
vdd_cpu: sd0 {
regulator-name = "vdd_cpu";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1250000>;
regulator-coupled-with = <&vdd_core>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
regulator-always-on;
regulator-boot-on;
nvidia,tegra-cpu-regulator;
};
vdd_core: sd1 {
regulator-name = "vdd_core";
regulator-min-microvolt = <950000>;
regulator-max-microvolt = <1350000>;
regulator-coupled-with = <&vdd_cpu>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
regulator-always-on;
regulator-boot-on;
nvidia,tegra-core-regulator;
};
vdd_1v8: sd2 {
regulator-name = "vdd_gen1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
vdd_1v35: sd3 {
regulator-name = "vdd_ddr3l_1v35";
regulator-min-microvolt = <1350000>;
regulator-max-microvolt = <1350000>;
regulator-always-on;
regulator-boot-on;
};
ldo0 {
regulator-name = "vdd_ddr_hs";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
regulator-boot-on;
};
ldo2 {
regulator-name = "vdd_ddr_rx";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
vcore_emmc: ldo3 {
regulator-name = "vcore_emmc";
regulator-min-microvolt = <2850000>;
regulator-max-microvolt = <3100000>;
regulator-always-on;
};
ldo4 {
regulator-name = "vdd_rtc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
ldo5 {
regulator-name = "vdd_camera";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo6 {
regulator-name = "vddio_sdmmc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
};
ldo7 {
regulator-name = "avdd_dsi_csi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
ldo8 {
regulator-name = "avdd_pll";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
};
};
};
vdd_3v3_sys: regulator@1 {
gpio = <&pmic 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
regulator@4 {
compatible = "regulator-fixed";
regulator-name = "avdd_usb";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
regulator-boot-on;
gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&vdd_3v3_sys>;
};
};

1565
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi Normal file
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149
arch/arm/boot/dts/tegra30-asus-nexus7-grouper-ti-pmic.dtsi Normal file
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@ -0,0 +1,149 @@
// SPDX-License-Identifier: GPL-2.0
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
/ {
i2c@7000d000 {
pmic: pmic@2d {
compatible = "ti,tps65911";
reg = <0x2d>;
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
interrupt-controller;
ti,en-gpio-sleep = <0 0 1 0 0 0 0 0 0>;
ti,system-power-controller;
ti,sleep-keep-ck32k;
ti,sleep-enable;
#gpio-cells = <2>;
gpio-controller;
vcc1-supply = <&vdd_5v0_sys>;
vcc2-supply = <&vdd_5v0_sys>;
vcc3-supply = <&vdd_1v8>;
vcc4-supply = <&vdd_5v0_sys>;
vcc5-supply = <&vdd_5v0_sys>;
vcc6-supply = <&vdd2_reg>;
vcc7-supply = <&vdd_5v0_sys>;
vccio-supply = <&vdd_5v0_sys>;
regulators {
vdd1 {
regulator-name = "vddio_ddr_1v2";
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <1500000>;
regulator-always-on;
regulator-boot-on;
ti,regulator-ext-sleep-control = <8>;
};
vdd2_reg: vdd2 {
regulator-name = "vdd2_1v2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
};
vdd_cpu: vddctrl {
regulator-name = "vdd_cpu,vdd_sys";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1250000>;
regulator-coupled-with = <&vdd_core>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
regulator-always-on;
ti,regulator-ext-sleep-control = <1>;
nvidia,tegra-cpu-regulator;
};
vdd_1v8: vio {
regulator-name = "vdd_1v8_gen";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
vcore_emmc: ldo1 {
regulator-name = "vdd_pexa,vdd_pexb";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
ldo2 {
regulator-name = "vdd_sata,avdd_plle";
regulator-min-microvolt = <1050000>;
regulator-max-microvolt = <1050000>;
};
/* LDO3 is not connected to anything */
ldo4 {
regulator-name = "vdd_rtc";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
ldo5 {
regulator-name = "vddio_sdmmc,avdd_vdac";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo6 {
regulator-name = "avdd_dsi_csi,pwrdet_mipi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
};
ldo7 {
regulator-name = "vdd_pllm,x,u,a_p_c_s";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
regulator-boot-on;
ti,regulator-ext-sleep-control = <8>;
};
ldo8 {
regulator-name = "vdd_ddr_hs";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-always-on;
ti,regulator-ext-sleep-control = <8>;
};
};
};
vdd_core: core-regulator@60 {
compatible = "ti,tps62361";
reg = <0x60>;
regulator-name = "tps62361-vout";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1350000>;
regulator-coupled-with = <&vdd_cpu>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
regulator-boot-on;
regulator-always-on;
ti,enable-vout-discharge;
ti,vsel0-state-high;
ti,vsel1-state-high;
nvidia,tegra-core-regulator;
};
};
vdd_3v3_sys: regulator@1 {
gpio = <&pmic 7 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};

149
arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi Normal file
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@ -0,0 +1,149 @@
// SPDX-License-Identifier: GPL-2.0
#include "tegra30-asus-nexus7-grouper-common.dtsi"
#include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
/ {
compatible = "asus,grouper", "nvidia,tegra30";
display-panel {
panel-timing {
clock-frequency = <68000000>;
hactive = <800>;
vactive = <1280>;
hfront-porch = <24>;
hback-porch = <32>;
hsync-len = <24>;
vsync-len = <1>;
vfront-porch = <5>;
vback-porch = <32>;
};
};
pinmux@70000868 {
state_default: pinmux {
lcd_dc1_pd2 {
nvidia,pins = "lcd_dc1_pd2";
nvidia,function = "displaya";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
lcd_pwr2_pc6 {
nvidia,pins = "lcd_pwr2_pc6";
nvidia,function = "displaya";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
spi2_cs2_n_pw3 {
nvidia,pins = "spi2_cs2_n_pw3";
nvidia,function = "spi2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
spi1_sck_px5 {
nvidia,pins = "spi1_sck_px5";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pu5 {
nvidia,pins = "pu5";
nvidia,function = "pwm2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
spi1_miso_px7 {
nvidia,pins = "spi1_miso_px7";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
spi2_mosi_px0 {
nvidia,pins = "spi2_mosi_px0";
nvidia,function = "spi2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
kb_row7_pr7 {
nvidia,pins = "kb_row7_pr7";
nvidia,function = "kbc";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
pu3 {
nvidia,pins = "pu3";
nvidia,function = "rsvd4";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pu4 {
nvidia,pins = "pu4";
nvidia,function = "pwm1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
kb_row15_ps7 {
nvidia,pins = "kb_row15_ps7";
nvidia,function = "kbc";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
kb_row3_pr3 {
nvidia,pins = "kb_row3_pr3";
nvidia,function = "kbc";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
kb_row13_ps5 {
nvidia,pins = "kb_row13_ps5";
nvidia,function = "kbc";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
gmi_wp_n_pc7 {
nvidia,pins = "gmi_wp_n_pc7",
"gmi_wait_pi7",
"gmi_cs4_n_pk2",
"gmi_cs3_n_pk4";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
gmi_cs6_n_pi3 {
nvidia,pins = "gmi_cs6_n_pi3";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
};
};
i2c@7000c500 {
nfc@28 {
compatible = "nxp,pn544-i2c";
reg = <0x28>;
clock-frequency = <100000>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(X, 0) IRQ_TYPE_EDGE_RISING>;
enable-gpios = <&gpio TEGRA_GPIO(S, 7) GPIO_ACTIVE_HIGH>;
firmware-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>;
};
};
};

9
arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-E1565.dts Normal file
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@ -0,0 +1,9 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "tegra30-asus-nexus7-grouper-maxim-pmic.dtsi"
#include "tegra30-asus-nexus7-tilapia.dtsi"
/ {
model = "ASUS Google Nexus 7 (Project Bach / ME370TG) E1565";
};

325
arch/arm/boot/dts/tegra30-asus-nexus7-tilapia-memory-timings.dtsi Normal file
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@ -0,0 +1,325 @@
// SPDX-License-Identifier: GPL-2.0
#include "tegra30-asus-nexus7-grouper-memory-timings.dtsi"
/ {
/*
* Tilapia's memory timings are pretty much the same as the Grouper's
* ones. There are few minor tunings made for a higher clock rates,
* these differentiating timings are overridden here for Tilapia.
*/
memory-controller@7000f400 {
emc-timings-0 {
timing-667000000 {
clock-frequency = <667000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100002>;
nvidia,emc-mode-2 = <0x80200018>;
nvidia,emc-mode-reset = <0x80000b71>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = <
0x0000001f /* EMC_RC */
0x00000069 /* EMC_RFC */
0x00000017 /* EMC_RAS */
0x00000007 /* EMC_RP */
0x00000005 /* EMC_R2W */
0x0000000c /* EMC_W2R */
0x00000003 /* EMC_R2P */
0x00000011 /* EMC_W2P */
0x00000007 /* EMC_RD_RCD */
0x00000007 /* EMC_WR_RCD */
0x00000002 /* EMC_RRD */
0x00000001 /* EMC_REXT */
0x00000000 /* EMC_WEXT */
0x00000007 /* EMC_WDV */
0x0000000b /* EMC_QUSE */
0x00000009 /* EMC_QRST */
0x0000000b /* EMC_QSAFE */
0x00000011 /* EMC_RDV */
0x00001412 /* EMC_REFRESH */
0x00000000 /* EMC_BURST_REFRESH_NUM */
0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
0x00000002 /* EMC_PDEX2WR */
0x0000000e /* EMC_PDEX2RD */
0x00000001 /* EMC_PCHG2PDEN */
0x00000000 /* EMC_ACT2PDEN */
0x0000000c /* EMC_AR2PDEN */
0x00000016 /* EMC_RW2PDEN */
0x00000072 /* EMC_TXSR */
0x00000200 /* EMC_TXSRDLL */
0x00000005 /* EMC_TCKE */
0x00000015 /* EMC_TFAW */
0x00000000 /* EMC_TRPAB */
0x00000006 /* EMC_TCLKSTABLE */
0x00000007 /* EMC_TCLKSTOP */
0x00001453 /* EMC_TREFBW */
0x0000000c /* EMC_QUSE_EXTRA */
0x00000004 /* EMC_FBIO_CFG6 */
0x00000000 /* EMC_ODT_WRITE */
0x00000000 /* EMC_ODT_READ */
0x00005088 /* EMC_FBIO_CFG5 */
0xf00b0191 /* EMC_CFG_DIG_DLL */
0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
0x00000008 /* EMC_DLL_XFORM_DQS0 */
0x00000008 /* EMC_DLL_XFORM_DQS1 */
0x00000008 /* EMC_DLL_XFORM_DQS2 */
0x00000008 /* EMC_DLL_XFORM_DQS3 */
0x0000000a /* EMC_DLL_XFORM_DQS4 */
0x0000000a /* EMC_DLL_XFORM_DQS5 */
0x0000000a /* EMC_DLL_XFORM_DQS6 */
0x0000000a /* EMC_DLL_XFORM_DQS7 */
0x00000000 /* EMC_DLL_XFORM_QUSE0 */
0x00000000 /* EMC_DLL_XFORM_QUSE1 */
0x00000000 /* EMC_DLL_XFORM_QUSE2 */
0x00000000 /* EMC_DLL_XFORM_QUSE3 */
0x00000000 /* EMC_DLL_XFORM_QUSE4 */
0x00000000 /* EMC_DLL_XFORM_QUSE5 */
0x00000000 /* EMC_DLL_XFORM_QUSE6 */
0x00000000 /* EMC_DLL_XFORM_QUSE7 */
0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
0x0000000c /* EMC_DLL_XFORM_DQ0 */
0x0000000c /* EMC_DLL_XFORM_DQ1 */
0x0000000c /* EMC_DLL_XFORM_DQ2 */
0x0000000c /* EMC_DLL_XFORM_DQ3 */
0x000002a0 /* EMC_XM2CMDPADCTRL */
0x0800013d /* EMC_XM2DQSPADCTRL2 */
0x22220000 /* EMC_XM2DQPADCTRL2 */
0x77fff884 /* EMC_XM2CLKPADCTRL */
0x01f1f501 /* EMC_XM2COMPPADCTRL */
0x07077404 /* EMC_XM2VTTGENPADCTRL */
0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
0x080001e8 /* EMC_XM2QUSEPADCTRL */
0x08000021 /* EMC_XM2DQSPADCTRL3 */
0x00000802 /* EMC_CTT_TERM_CTRL */
0x00020000 /* EMC_ZCAL_INTERVAL */
0x00000100 /* EMC_ZCAL_WAIT_CNT */
0x0156000c /* EMC_MRS_WAIT_CNT */
0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
0x00000000 /* EMC_CTT */
0x00000000 /* EMC_CTT_DURATION */
0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
0xe8000000 /* EMC_FBIO_SPARE */
0xff00ff49 /* EMC_CFG_RSV */
>;
};
};
emc-timings-1 {
timing-333500000 {
clock-frequency = <333500000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100002>;
nvidia,emc-mode-2 = <0x80200000>;
nvidia,emc-mode-reset = <0x80000321>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-configuration = <
0x0000000f /* EMC_RC */
0x00000034 /* EMC_RFC */
0x0000000a /* EMC_RAS */
0x00000003 /* EMC_RP */
0x00000003 /* EMC_R2W */
0x00000008 /* EMC_W2R */
0x00000002 /* EMC_R2P */
0x00000009 /* EMC_W2P */
0x00000003 /* EMC_RD_RCD */
0x00000003 /* EMC_WR_RCD */
0x00000002 /* EMC_RRD */
0x00000001 /* EMC_REXT */
0x00000000 /* EMC_WEXT */
0x00000004 /* EMC_WDV */
0x00000006 /* EMC_QUSE */
0x00000004 /* EMC_QRST */
0x0000000a /* EMC_QSAFE */
0x0000000c /* EMC_RDV */
0x000009e9 /* EMC_REFRESH */
0x00000000 /* EMC_BURST_REFRESH_NUM */
0x0000027a /* EMC_PRE_REFRESH_REQ_CNT */
0x00000001 /* EMC_PDEX2WR */
0x00000008 /* EMC_PDEX2RD */
0x00000001 /* EMC_PCHG2PDEN */
0x00000000 /* EMC_ACT2PDEN */
0x00000007 /* EMC_AR2PDEN */
0x0000000e /* EMC_RW2PDEN */
0x00000039 /* EMC_TXSR */
0x00000200 /* EMC_TXSRDLL */
0x00000004 /* EMC_TCKE */
0x0000000a /* EMC_TFAW */
0x00000000 /* EMC_TRPAB */
0x00000004 /* EMC_TCLKSTABLE */
0x00000005 /* EMC_TCLKSTOP */
0x00000a2a /* EMC_TREFBW */
0x00000000 /* EMC_QUSE_EXTRA */
0x00000004 /* EMC_FBIO_CFG6 */
0x00000000 /* EMC_ODT_WRITE */
0x00000000 /* EMC_ODT_READ */
0x00007088 /* EMC_FBIO_CFG5 */
0x002600a4 /* EMC_CFG_DIG_DLL */
0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
0x0003c000 /* EMC_DLL_XFORM_DQS0 */
0x0003c000 /* EMC_DLL_XFORM_DQS1 */
0x0003c000 /* EMC_DLL_XFORM_DQS2 */
0x0003c000 /* EMC_DLL_XFORM_DQS3 */
0x00014000 /* EMC_DLL_XFORM_DQS4 */
0x00014000 /* EMC_DLL_XFORM_DQS5 */
0x00014000 /* EMC_DLL_XFORM_DQS6 */
0x00014000 /* EMC_DLL_XFORM_DQS7 */
0x00000000 /* EMC_DLL_XFORM_QUSE0 */
0x00000000 /* EMC_DLL_XFORM_QUSE1 */
0x00000000 /* EMC_DLL_XFORM_QUSE2 */
0x00000000 /* EMC_DLL_XFORM_QUSE3 */
0x00000000 /* EMC_DLL_XFORM_QUSE4 */
0x00000000 /* EMC_DLL_XFORM_QUSE5 */
0x00000000 /* EMC_DLL_XFORM_QUSE6 */
0x00000000 /* EMC_DLL_XFORM_QUSE7 */
0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
0x00048000 /* EMC_DLL_XFORM_DQ0 */
0x00048000 /* EMC_DLL_XFORM_DQ1 */
0x00048000 /* EMC_DLL_XFORM_DQ2 */
0x00048000 /* EMC_DLL_XFORM_DQ3 */
0x000002a0 /* EMC_XM2CMDPADCTRL */
0x0800013d /* EMC_XM2DQSPADCTRL2 */
0x00000000 /* EMC_XM2DQPADCTRL2 */
0x77fff884 /* EMC_XM2CLKPADCTRL */
0x01f1f508 /* EMC_XM2COMPPADCTRL */
0x05057404 /* EMC_XM2VTTGENPADCTRL */
0x54000007 /* EMC_XM2VTTGENPADCTRL2 */
0x080001e8 /* EMC_XM2QUSEPADCTRL */
0x08000021 /* EMC_XM2DQSPADCTRL3 */
0x00000802 /* EMC_CTT_TERM_CTRL */
0x00020000 /* EMC_ZCAL_INTERVAL */
0x00000100 /* EMC_ZCAL_WAIT_CNT */
0x018b000c /* EMC_MRS_WAIT_CNT */
0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
0x00000000 /* EMC_CTT */
0x00000000 /* EMC_CTT_DURATION */
0x800014d4 /* EMC_DYN_SELF_REF_CONTROL */
0xe8000000 /* EMC_FBIO_SPARE */
0xff00ff89 /* EMC_CFG_RSV */
>;
};
timing-667000000 {
clock-frequency = <667000000>;
nvidia,emc-auto-cal-interval = <0x001fffff>;
nvidia,emc-mode-1 = <0x80100002>;
nvidia,emc-mode-2 = <0x80200018>;
nvidia,emc-mode-reset = <0x80000b71>;
nvidia,emc-zcal-cnt-long = <0x00000040>;
nvidia,emc-cfg-periodic-qrst;
nvidia,emc-configuration = <
0x00000020 /* EMC_RC */
0x0000006a /* EMC_RFC */
0x00000017 /* EMC_RAS */
0x00000007 /* EMC_RP */
0x00000005 /* EMC_R2W */
0x0000000c /* EMC_W2R */
0x00000003 /* EMC_R2P */
0x00000011 /* EMC_W2P */
0x00000007 /* EMC_RD_RCD */
0x00000007 /* EMC_WR_RCD */
0x00000002 /* EMC_RRD */
0x00000001 /* EMC_REXT */
0x00000000 /* EMC_WEXT */
0x00000007 /* EMC_WDV */
0x0000000a /* EMC_QUSE */
0x00000009 /* EMC_QRST */
0x0000000b /* EMC_QSAFE */
0x00000011 /* EMC_RDV */
0x00001412 /* EMC_REFRESH */
0x00000000 /* EMC_BURST_REFRESH_NUM */
0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
0x00000002 /* EMC_PDEX2WR */
0x0000000e /* EMC_PDEX2RD */
0x00000001 /* EMC_PCHG2PDEN */
0x00000000 /* EMC_ACT2PDEN */
0x0000000c /* EMC_AR2PDEN */
0x00000016 /* EMC_RW2PDEN */
0x00000072 /* EMC_TXSR */
0x00000200 /* EMC_TXSRDLL */
0x00000005 /* EMC_TCKE */
0x00000015 /* EMC_TFAW */
0x00000000 /* EMC_TRPAB */
0x00000006 /* EMC_TCLKSTABLE */
0x00000007 /* EMC_TCLKSTOP */
0x00001453 /* EMC_TREFBW */
0x0000000b /* EMC_QUSE_EXTRA */
0x00000006 /* EMC_FBIO_CFG6 */
0x00000000 /* EMC_ODT_WRITE */
0x00000000 /* EMC_ODT_READ */
0x00005088 /* EMC_FBIO_CFG5 */
0xf00b0191 /* EMC_CFG_DIG_DLL */
0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
0x00000008 /* EMC_DLL_XFORM_DQS0 */
0x00000008 /* EMC_DLL_XFORM_DQS1 */
0x00000008 /* EMC_DLL_XFORM_DQS2 */
0x00000008 /* EMC_DLL_XFORM_DQS3 */
0x0000000a /* EMC_DLL_XFORM_DQS4 */
0x0000000a /* EMC_DLL_XFORM_DQS5 */
0x0000000a /* EMC_DLL_XFORM_DQS6 */
0x0000000a /* EMC_DLL_XFORM_DQS7 */
0x00018000 /* EMC_DLL_XFORM_QUSE0 */
0x00018000 /* EMC_DLL_XFORM_QUSE1 */
0x00018000 /* EMC_DLL_XFORM_QUSE2 */
0x00018000 /* EMC_DLL_XFORM_QUSE3 */
0x00000000 /* EMC_DLL_XFORM_QUSE4 */
0x00000000 /* EMC_DLL_XFORM_QUSE5 */
0x00000000 /* EMC_DLL_XFORM_QUSE6 */
0x00000000 /* EMC_DLL_XFORM_QUSE7 */
0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
0x0000000a /* EMC_DLL_XFORM_DQ0 */
0x0000000a /* EMC_DLL_XFORM_DQ1 */
0x0000000a /* EMC_DLL_XFORM_DQ2 */
0x0000000a /* EMC_DLL_XFORM_DQ3 */
0x000002a0 /* EMC_XM2CMDPADCTRL */
0x0800013d /* EMC_XM2DQSPADCTRL2 */
0x22220000 /* EMC_XM2DQPADCTRL2 */
0x77fff884 /* EMC_XM2CLKPADCTRL */
0x01f1f501 /* EMC_XM2COMPPADCTRL */
0x07077404 /* EMC_XM2VTTGENPADCTRL */
0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
0x080001e8 /* EMC_XM2QUSEPADCTRL */
0x0c000021 /* EMC_XM2DQSPADCTRL3 */
0x00000802 /* EMC_CTT_TERM_CTRL */
0x00020000 /* EMC_ZCAL_INTERVAL */
0x00000100 /* EMC_ZCAL_WAIT_CNT */
0x0155000c /* EMC_MRS_WAIT_CNT */
0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
0x00000000 /* EMC_CTT */
0x00000000 /* EMC_CTT_DURATION */
0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
0xe8000000 /* EMC_FBIO_SPARE */
0xff00ff49 /* EMC_CFG_RSV */
>;
};
};
};
};

235
arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi Normal file
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@ -0,0 +1,235 @@
// SPDX-License-Identifier: GPL-2.0
#include "tegra30-asus-nexus7-grouper-common.dtsi"
#include "tegra30-asus-nexus7-tilapia-memory-timings.dtsi"
/ {
compatible = "asus,tilapia", "asus,grouper", "nvidia,tegra30";
display-panel {
enable-gpios = <&gpio TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>;
panel-timing {
clock-frequency = <81750000>;
hactive = <800>;
vactive = <1280>;
hfront-porch = <64>;
hback-porch = <128>;
hsync-len = <64>;
vsync-len = <1>;
vfront-porch = <5>;
vback-porch = <2>;
};
};
gpio@6000d000 {
init-mode-3g {
gpio-hog;
gpios = <TEGRA_GPIO(D, 2) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(W, 3) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(P, 1) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(X, 5) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(U, 5) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(X, 7) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(X, 0) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(EE, 1) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(Y, 2) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(Y, 3) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(U, 3) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(N, 1) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(N, 2) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(N, 0) GPIO_ACTIVE_HIGH>,
<TEGRA_GPIO(N, 3) GPIO_ACTIVE_HIGH>;
output-low;
};
};
pinmux@70000868 {
state_default: pinmux {
lcd_dc1_pd2 {
nvidia,pins = "lcd_dc1_pd2";
nvidia,function = "displaya";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
lcd_pwr2_pc6 {
nvidia,pins = "lcd_pwr2_pc6";
nvidia,function = "displaya";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
spi2_cs2_n_pw3 {
nvidia,pins = "spi2_cs2_n_pw3";
nvidia,function = "spi2";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
dap3_din_pp1 {
nvidia,pins = "dap3_din_pp1";
nvidia,function = "i2s2";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
spi1_sck_px5 {
nvidia,pins = "spi1_sck_px5";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
pu5 {
nvidia,pins = "pu5";
nvidia,function = "pwm2";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
spi1_miso_px7 {
nvidia,pins = "spi1_miso_px7";
nvidia,function = "spi1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
spi2_mosi_px0 {
nvidia,pins = "spi2_mosi_px0";
nvidia,function = "spi2";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
clk3_req_pee1 {
nvidia,pins = "clk3_req_pee1";
nvidia,function = "dev3";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
ulpi_nxt_py2 {
nvidia,pins = "ulpi_nxt_py2";
nvidia,function = "uartd";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
ulpi_stp_py3 {
nvidia,pins = "ulpi_stp_py3";
nvidia,function = "uartd";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
kb_row7_pr7 {
nvidia,pins = "kb_row7_pr7";
nvidia,function = "kbc";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
pu4 {
nvidia,pins = "pu4";
nvidia,function = "pwm1";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
pu3 {
nvidia,pins = "pu3";
nvidia,function = "rsvd4";
nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
kb_row15_ps7 {
nvidia,pins = "kb_row15_ps7";
nvidia,function = "kbc";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
dap3_sclk_pp3 {
nvidia,pins = "dap3_sclk_pp3";
nvidia,function = "i2s2";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_DISABLE>;
};
kb_row3_pr3 {
nvidia,pins = "kb_row3_pr3",
"kb_row13_ps5";
nvidia,function = "kbc";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
kb_row13_ps5 {
nvidia,pins = "kb_row13_ps5";
nvidia,function = "kbc";
nvidia,pull = <TEGRA_PIN_PULL_UP>;
nvidia,tristate = <TEGRA_PIN_DISABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
gmi_wp_n_pc7 {
nvidia,pins = "gmi_wp_n_pc7",
"gmi_wait_pi7",
"gmi_cs4_n_pk2",
"gmi_cs3_n_pk4";
nvidia,function = "rsvd1";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
gmi_cs6_n_pi3 {
nvidia,pins = "gmi_cs6_n_pi3";
nvidia,function = "gmi";
nvidia,pull = <TEGRA_PIN_PULL_NONE>;
nvidia,tristate = <TEGRA_PIN_ENABLE>;
nvidia,enable-input = <TEGRA_PIN_ENABLE>;
};
};
};
i2c@7000c500 {
proximity-sensor@28 {
compatible = "microchip,cap1106";
reg = <0x28>;
/*
* Binding doesn't support specifying linux,input-type
* and this results in unwanted key-presses handled by
* applications, hence keep it disabled for now.
*/
status = "disabled";
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(R, 3) IRQ_TYPE_LEVEL_HIGH>;
linux,keycodes = <KEY_RESERVED>,
<KEY_RESERVED>,
<KEY_RESERVED>,
<KEY_RESERVED>,
<KEY_RESERVED>,
<SW_FRONT_PROXIMITY>;
};
nfc@2a {
compatible = "nxp,pn544-i2c";
reg = <0x2a>;
clock-frequency = <100000>;
interrupt-parent = <&gpio>;
interrupts = <TEGRA_GPIO(S, 7) IRQ_TYPE_EDGE_RISING>;
enable-gpios = <&gpio TEGRA_GPIO(P, 0) GPIO_ACTIVE_HIGH>;
firmware-gpios = <&gpio TEGRA_GPIO(P, 3) GPIO_ACTIVE_HIGH>;
};
};
};