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PCI/DPC: Cache DPC capabilities in pci_init_capabilities()
Since Error Disconnect Recover needs to use DPC error handling routines even if the OS doesn't have control of DPC, move the initalization and caching of DPC capabilities from the DPC driver to pci_init_capabilities(). Link: https://lore.kernel.org/r/5888380657c8b9551675b5dbd48e370e4fd2703d.1585000084.git.sathyanarayanan.kuppuswamy@linux.intel.com Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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@ -448,9 +448,11 @@ void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
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#ifdef CONFIG_PCIE_DPC
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#ifdef CONFIG_PCIE_DPC
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void pci_save_dpc_state(struct pci_dev *dev);
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void pci_save_dpc_state(struct pci_dev *dev);
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void pci_restore_dpc_state(struct pci_dev *dev);
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void pci_restore_dpc_state(struct pci_dev *dev);
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void pci_dpc_init(struct pci_dev *pdev);
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#else
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#else
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static inline void pci_save_dpc_state(struct pci_dev *dev) {}
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static inline void pci_save_dpc_state(struct pci_dev *dev) {}
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static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
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static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
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static inline void pci_dpc_init(struct pci_dev *pdev) {}
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#endif
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#endif
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#ifdef CONFIG_PCI_ATS
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#ifdef CONFIG_PCI_ATS
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@ -249,6 +249,27 @@ static irqreturn_t dpc_irq(int irq, void *context)
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return IRQ_HANDLED;
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return IRQ_HANDLED;
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}
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}
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void pci_dpc_init(struct pci_dev *pdev)
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{
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u16 cap;
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pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
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if (!pdev->dpc_cap)
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return;
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pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
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if (!(cap & PCI_EXP_DPC_CAP_RP_EXT))
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return;
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pdev->dpc_rp_extensions = true;
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pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
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if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
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pci_err(pdev, "RP PIO log size %u is invalid\n",
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pdev->dpc_rp_log_size);
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pdev->dpc_rp_log_size = 0;
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}
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}
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#define FLAG(x, y) (((x) & (y)) ? '+' : '-')
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#define FLAG(x, y) (((x) & (y)) ? '+' : '-')
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static int dpc_probe(struct pcie_device *dev)
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static int dpc_probe(struct pcie_device *dev)
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{
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{
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@ -260,8 +281,6 @@ static int dpc_probe(struct pcie_device *dev)
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if (pcie_aer_get_firmware_first(pdev) && !pcie_ports_dpc_native)
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if (pcie_aer_get_firmware_first(pdev) && !pcie_ports_dpc_native)
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return -ENOTSUPP;
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return -ENOTSUPP;
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pdev->dpc_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DPC);
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status = devm_request_threaded_irq(device, dev->irq, dpc_irq,
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status = devm_request_threaded_irq(device, dev->irq, dpc_irq,
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dpc_handler, IRQF_SHARED,
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dpc_handler, IRQF_SHARED,
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"pcie-dpc", pdev);
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"pcie-dpc", pdev);
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@ -274,16 +293,6 @@ static int dpc_probe(struct pcie_device *dev)
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pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
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pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CAP, &cap);
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pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
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pci_read_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, &ctl);
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pdev->dpc_rp_extensions = (cap & PCI_EXP_DPC_CAP_RP_EXT) ? 1 : 0;
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if (pdev->dpc_rp_extensions) {
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pdev->dpc_rp_log_size = (cap & PCI_EXP_DPC_RP_PIO_LOG_SIZE) >> 8;
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if (pdev->dpc_rp_log_size < 4 || pdev->dpc_rp_log_size > 9) {
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pci_err(pdev, "RP PIO log size %u is invalid\n",
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pdev->dpc_rp_log_size);
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pdev->dpc_rp_log_size = 0;
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}
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}
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ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN;
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ctl = (ctl & 0xfff4) | PCI_EXP_DPC_CTL_EN_FATAL | PCI_EXP_DPC_CTL_INT_EN;
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pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);
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pci_write_config_word(pdev, pdev->dpc_cap + PCI_EXP_DPC_CTL, ctl);
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@ -2329,6 +2329,7 @@ static void pci_init_capabilities(struct pci_dev *dev)
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pci_enable_acs(dev); /* Enable ACS P2P upstream forwarding */
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pci_enable_acs(dev); /* Enable ACS P2P upstream forwarding */
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pci_ptm_init(dev); /* Precision Time Measurement */
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pci_ptm_init(dev); /* Precision Time Measurement */
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pci_aer_init(dev); /* Advanced Error Reporting */
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pci_aer_init(dev); /* Advanced Error Reporting */
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pci_dpc_init(dev); /* Downstream Port Containment */
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pcie_report_downtraining(dev);
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pcie_report_downtraining(dev);
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