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PCI: artpec6: Add register accessors
Add device-specific register accessors for consistency across host drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Jesper Nilsson <jesper.nilsson@axis.com>
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@ -65,6 +65,19 @@ struct artpec6_pcie {
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#define ARTPEC6_CPU_TO_BUS_ADDR 0x0fffffff
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static u32 artpec6_pcie_readl(struct artpec6_pcie *artpec6_pcie, u32 offset)
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{
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u32 val;
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regmap_read(artpec6_pcie->regmap, offset, &val);
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return val;
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}
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static void artpec6_pcie_writel(struct artpec6_pcie *artpec6_pcie, u32 offset, u32 val)
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{
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regmap_write(artpec6_pcie->regmap, offset, val);
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}
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static int artpec6_pcie_establish_link(struct pcie_port *pp)
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{
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struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pp);
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@ -72,11 +85,11 @@ static int artpec6_pcie_establish_link(struct pcie_port *pp)
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unsigned int retries;
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/* Hold DW core in reset */
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regmap_read(artpec6_pcie->regmap, PCIECFG, &val);
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val |= PCIECFG_CORE_RESET_REQ;
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regmap_write(artpec6_pcie->regmap, PCIECFG, val);
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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regmap_read(artpec6_pcie->regmap, PCIECFG, &val);
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val |= PCIECFG_RISRCREN | /* Receiver term. 50 Ohm */
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PCIECFG_MODE_TX_DRV_EN |
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PCIECFG_CISRREN | /* Reference clock term. 100 Ohm */
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@ -84,27 +97,27 @@ static int artpec6_pcie_establish_link(struct pcie_port *pp)
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val |= PCIECFG_REFCLK_ENABLE;
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val &= ~PCIECFG_DBG_OEN;
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val &= ~PCIECFG_CLKREQ_B;
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regmap_write(artpec6_pcie->regmap, PCIECFG, val);
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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usleep_range(5000, 6000);
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regmap_read(artpec6_pcie->regmap, NOCCFG, &val);
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val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
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val |= NOCCFG_ENABLE_CLK_PCIE;
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regmap_write(artpec6_pcie->regmap, NOCCFG, val);
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artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
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usleep_range(20, 30);
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regmap_read(artpec6_pcie->regmap, PCIECFG, &val);
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val |= PCIECFG_PCLK_ENABLE | PCIECFG_PLL_ENABLE;
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regmap_write(artpec6_pcie->regmap, PCIECFG, val);
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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usleep_range(6000, 7000);
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regmap_read(artpec6_pcie->regmap, NOCCFG, &val);
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val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
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val &= ~NOCCFG_POWER_PCIE_IDLEREQ;
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regmap_write(artpec6_pcie->regmap, NOCCFG, val);
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artpec6_pcie_writel(artpec6_pcie, NOCCFG, val);
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retries = 50;
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do {
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usleep_range(1000, 2000);
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regmap_read(artpec6_pcie->regmap, NOCCFG, &val);
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val = artpec6_pcie_readl(artpec6_pcie, NOCCFG);
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retries--;
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} while (retries &&
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(val & (NOCCFG_POWER_PCIE_IDLEACK | NOCCFG_POWER_PCIE_IDLE)));
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@ -117,9 +130,9 @@ static int artpec6_pcie_establish_link(struct pcie_port *pp)
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} while (retries && !(val & PHY_COSPLLLOCK));
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/* Take DW core out of reset */
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regmap_read(artpec6_pcie->regmap, PCIECFG, &val);
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val &= ~PCIECFG_CORE_RESET_REQ;
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regmap_write(artpec6_pcie->regmap, PCIECFG, val);
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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usleep_range(100, 200);
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/*
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@ -137,9 +150,9 @@ static int artpec6_pcie_establish_link(struct pcie_port *pp)
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dw_pcie_setup_rc(pp);
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/* assert LTSSM enable */
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regmap_read(artpec6_pcie->regmap, PCIECFG, &val);
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val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
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val |= PCIECFG_LTSSM_ENABLE;
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regmap_write(artpec6_pcie->regmap, PCIECFG, val);
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artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
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/* check if the link is up or not */
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if (!dw_pcie_wait_for_link(pp))
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