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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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Merge branch 'drm-fixes-4.20' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
Fixes for 4.20: - Stability fixes for new polaris variants (e.g., RX590) - New vega pci ids - Vega20 smu fix - Ctx locking fix Signed-off-by: Dave Airlie <airlied@redhat.com> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181212203022.3054-1-alexander.deucher@amd.com
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commit
26eacb788b
@ -330,7 +330,9 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
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case CHIP_TOPAZ:
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if (((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x81)) ||
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((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0x83)) ||
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((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87))) {
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((adev->pdev->device == 0x6907) && (adev->pdev->revision == 0x87)) ||
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((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD1)) ||
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((adev->pdev->device == 0x6900) && (adev->pdev->revision == 0xD3))) {
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info->is_kicker = true;
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strcpy(fw_name, "amdgpu/topaz_k_smc.bin");
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} else
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@ -351,7 +353,6 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
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if (type == CGS_UCODE_ID_SMU) {
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if (((adev->pdev->device == 0x67ef) &&
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((adev->pdev->revision == 0xe0) ||
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(adev->pdev->revision == 0xe2) ||
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(adev->pdev->revision == 0xe5))) ||
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((adev->pdev->device == 0x67ff) &&
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((adev->pdev->revision == 0xcf) ||
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@ -359,8 +360,13 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
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(adev->pdev->revision == 0xff)))) {
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info->is_kicker = true;
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strcpy(fw_name, "amdgpu/polaris11_k_smc.bin");
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} else
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} else if ((adev->pdev->device == 0x67ef) &&
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(adev->pdev->revision == 0xe2)) {
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info->is_kicker = true;
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strcpy(fw_name, "amdgpu/polaris11_k2_smc.bin");
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} else {
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strcpy(fw_name, "amdgpu/polaris11_smc.bin");
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}
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} else if (type == CGS_UCODE_ID_SMU_SK) {
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strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin");
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}
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@ -375,17 +381,35 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
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(adev->pdev->revision == 0xe7) ||
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(adev->pdev->revision == 0xef))) ||
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((adev->pdev->device == 0x6fdf) &&
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(adev->pdev->revision == 0xef))) {
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((adev->pdev->revision == 0xef) ||
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(adev->pdev->revision == 0xff)))) {
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info->is_kicker = true;
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strcpy(fw_name, "amdgpu/polaris10_k_smc.bin");
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} else
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} else if ((adev->pdev->device == 0x67df) &&
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((adev->pdev->revision == 0xe1) ||
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(adev->pdev->revision == 0xf7))) {
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info->is_kicker = true;
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strcpy(fw_name, "amdgpu/polaris10_k2_smc.bin");
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} else {
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strcpy(fw_name, "amdgpu/polaris10_smc.bin");
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}
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} else if (type == CGS_UCODE_ID_SMU_SK) {
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strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin");
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}
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break;
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case CHIP_POLARIS12:
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strcpy(fw_name, "amdgpu/polaris12_smc.bin");
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if (((adev->pdev->device == 0x6987) &&
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((adev->pdev->revision == 0xc0) ||
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(adev->pdev->revision == 0xc3))) ||
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((adev->pdev->device == 0x6981) &&
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((adev->pdev->revision == 0x00) ||
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(adev->pdev->revision == 0x01) ||
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(adev->pdev->revision == 0x10)))) {
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info->is_kicker = true;
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strcpy(fw_name, "amdgpu/polaris12_k_smc.bin");
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} else {
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strcpy(fw_name, "amdgpu/polaris12_smc.bin");
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}
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break;
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case CHIP_VEGAM:
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strcpy(fw_name, "amdgpu/vegam_smc.bin");
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@ -124,14 +124,14 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs
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goto free_chunk;
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}
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mutex_lock(&p->ctx->lock);
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/* skip guilty context job */
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if (atomic_read(&p->ctx->guilty) == 1) {
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ret = -ECANCELED;
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goto free_chunk;
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}
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mutex_lock(&p->ctx->lock);
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/* get chunks */
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chunk_array_user = u64_to_user_ptr(cs->in.chunks);
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if (copy_from_user(chunk_array, chunk_array_user,
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@ -872,7 +872,13 @@ static const struct pci_device_id pciidlist[] = {
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{0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
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{0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
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{0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
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{0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
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{0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
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{0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
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{0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
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{0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
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{0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
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{0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
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{0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
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/* Vega 12 */
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{0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
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@ -885,6 +891,7 @@ static const struct pci_device_id pciidlist[] = {
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{0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
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{0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
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{0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
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{0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
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{0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
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{0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
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/* Raven */
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@ -337,12 +337,19 @@ static const struct kfd_deviceid supported_devices[] = {
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{ 0x6864, &vega10_device_info }, /* Vega10 */
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{ 0x6867, &vega10_device_info }, /* Vega10 */
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{ 0x6868, &vega10_device_info }, /* Vega10 */
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{ 0x6869, &vega10_device_info }, /* Vega10 */
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{ 0x686A, &vega10_device_info }, /* Vega10 */
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{ 0x686B, &vega10_device_info }, /* Vega10 */
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{ 0x686C, &vega10_vf_device_info }, /* Vega10 vf*/
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{ 0x686D, &vega10_device_info }, /* Vega10 */
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{ 0x686E, &vega10_device_info }, /* Vega10 */
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{ 0x686F, &vega10_device_info }, /* Vega10 */
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{ 0x687F, &vega10_device_info }, /* Vega10 */
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{ 0x66a0, &vega20_device_info }, /* Vega20 */
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{ 0x66a1, &vega20_device_info }, /* Vega20 */
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{ 0x66a2, &vega20_device_info }, /* Vega20 */
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{ 0x66a3, &vega20_device_info }, /* Vega20 */
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{ 0x66a4, &vega20_device_info }, /* Vega20 */
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{ 0x66a7, &vega20_device_info }, /* Vega20 */
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{ 0x66af, &vega20_device_info } /* Vega20 */
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};
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@ -130,7 +130,7 @@ static void vega20_set_default_registry_data(struct pp_hwmgr *hwmgr)
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data->registry_data.disable_auto_wattman = 1;
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data->registry_data.auto_wattman_debug = 0;
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data->registry_data.auto_wattman_sample_period = 100;
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data->registry_data.fclk_gfxclk_ratio = 0x3F6CCCCD;
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data->registry_data.fclk_gfxclk_ratio = 0;
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data->registry_data.auto_wattman_threshold = 50;
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data->registry_data.gfxoff_controlled_by_driver = 1;
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data->gfxoff_allowed = false;
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@ -386,6 +386,8 @@ typedef uint16_t PPSMC_Result;
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#define PPSMC_MSG_AgmResetPsm ((uint16_t) 0x403)
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#define PPSMC_MSG_ReadVftCell ((uint16_t) 0x404)
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#define PPSMC_MSG_ApplyAvfsCksOffVoltage ((uint16_t) 0x415)
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#define PPSMC_MSG_GFX_CU_PG_ENABLE ((uint16_t) 0x280)
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#define PPSMC_MSG_GFX_CU_PG_DISABLE ((uint16_t) 0x281)
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#define PPSMC_MSG_GetCurrPkgPwr ((uint16_t) 0x282)
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@ -1985,6 +1985,12 @@ int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs);
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/* Apply avfs cks-off voltages to avoid the overshoot
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* when switching to the highest sclk frequency
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*/
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if (data->apply_avfs_cks_off_voltage)
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smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage);
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return 0;
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}
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@ -37,10 +37,13 @@ MODULE_FIRMWARE("amdgpu/fiji_smc.bin");
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MODULE_FIRMWARE("amdgpu/polaris10_smc.bin");
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MODULE_FIRMWARE("amdgpu/polaris10_smc_sk.bin");
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MODULE_FIRMWARE("amdgpu/polaris10_k_smc.bin");
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MODULE_FIRMWARE("amdgpu/polaris10_k2_smc.bin");
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MODULE_FIRMWARE("amdgpu/polaris11_smc.bin");
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MODULE_FIRMWARE("amdgpu/polaris11_smc_sk.bin");
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MODULE_FIRMWARE("amdgpu/polaris11_k_smc.bin");
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MODULE_FIRMWARE("amdgpu/polaris11_k2_smc.bin");
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MODULE_FIRMWARE("amdgpu/polaris12_smc.bin");
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MODULE_FIRMWARE("amdgpu/polaris12_k_smc.bin");
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MODULE_FIRMWARE("amdgpu/vegam_smc.bin");
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MODULE_FIRMWARE("amdgpu/vega10_smc.bin");
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MODULE_FIRMWARE("amdgpu/vega10_acg_smc.bin");
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