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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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staging: comedi: s626: remove WR7146 and SETVECT macros
The WR7146 macro relies on a local variable having a specific name. This macro is a wrapper around a writel() call. Remove the macro and just call writel() directly. The SETVEC macro uses the WR7146 macro so remove it as well and just do the writel() directly. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten
Greg Kroah-Hartman
parent
95bb798275
commit
25f8fd5e11
@ -169,10 +169,6 @@ static bool s626_mc_test(struct comedi_device *dev,
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return (val & cmd) ? true : false;
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}
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/* #define WR7146(REGARDS,CTRLWORD)
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writel(CTRLWORD,(uint32_t)(devpriv->base_addr+(REGARDS))) */
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#define WR7146(REGARDS, CTRLWORD) writel(CTRLWORD, devpriv->base_addr+(REGARDS))
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/* #define RR7146(REGARDS)
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readl((uint32_t)(devpriv->base_addr+(REGARDS))) */
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#define RR7146(REGARDS) readl(devpriv->base_addr+(REGARDS))
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@ -181,7 +177,6 @@ static bool s626_mc_test(struct comedi_device *dev,
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/* Write a time slot control record to TSL2. */
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#define VECTPORT(VECTNUM) (P_TSL2 + ((VECTNUM) << 2))
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#define SETVECT(VECTNUM, VECTVAL) WR7146(VECTPORT(VECTNUM), (VECTVAL))
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/* Code macros used for constructing I2C command bytes. */
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#define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
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@ -223,8 +218,8 @@ static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr)
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struct s626_private *devpriv = dev->private;
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uint16_t retval;
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/* Set up DEBI control register value in shadow RAM. */
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WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
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/* Set up DEBI control register value in shadow RAM */
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writel(DEBI_CMD_RDWORD | addr, devpriv->base_addr + P_DEBICMD);
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/* Execute the DEBI transfer. */
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DEBItransfer(dev);
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@ -241,9 +236,9 @@ static void DEBIwrite(struct comedi_device *dev, uint16_t addr, uint16_t wdata)
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{
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struct s626_private *devpriv = dev->private;
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/* Set up DEBI control register value in shadow RAM. */
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WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
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WR7146(P_DEBIAD, wdata);
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/* Set up DEBI control register value in shadow RAM */
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writel(DEBI_CMD_WRWORD | addr, devpriv->base_addr + P_DEBICMD);
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writel(wdata, devpriv->base_addr + P_DEBIAD);
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/* Execute the DEBI transfer. */
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DEBItransfer(dev);
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@ -258,16 +253,16 @@ static void DEBIreplace(struct comedi_device *dev, uint16_t addr, uint16_t mask,
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{
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struct s626_private *devpriv = dev->private;
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/* Copy target gate array register into P_DEBIAD register. */
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WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
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/* Copy target gate array register into P_DEBIAD register */
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writel(DEBI_CMD_RDWORD | addr, devpriv->base_addr + P_DEBICMD);
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/* Set up DEBI control reg value in shadow RAM. */
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DEBItransfer(dev); /* Execute the DEBI Read transfer. */
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/* Write back the modified image. */
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WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
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/* Set up DEBI control reg value in shadow RAM. */
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WR7146(P_DEBIAD, wdata | ((uint16_t) RR7146(P_DEBIAD) & mask));
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/* Write back the modified image */
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writel(DEBI_CMD_WRWORD | addr, devpriv->base_addr + P_DEBICMD);
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/* Set up DEBI control reg value in shadow RAM */
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writel(wdata | ((uint16_t) RR7146(P_DEBIAD) & mask),
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devpriv->base_addr + P_DEBIAD);
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/* Modify the register image. */
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DEBItransfer(dev); /* Execute the DEBI Write transfer. */
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}
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@ -278,8 +273,8 @@ static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val)
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{
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struct s626_private *devpriv = dev->private;
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/* Write I2C command to I2C Transfer Control shadow register. */
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WR7146(P_I2CCTRL, val);
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/* Write I2C command to I2C Transfer Control shadow register */
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writel(val, devpriv->base_addr + P_I2CCTRL);
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/*
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* Upload I2C shadow registers into working registers and
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@ -372,7 +367,7 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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/* Copy DAC setpoint value to DAC's output DMA buffer. */
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/* WR7146( (uint32_t)devpriv->pDacWBuf, val ); */
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/* writel(val, devpriv->base_addr + (uint32_t)devpriv->pDacWBuf); */
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*devpriv->pDacWBuf = val;
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/*
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@ -385,11 +380,12 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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/* While the DMA transfer is executing ... */
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/* Reset Audio2 output FIFO's underflow flag (along with any other
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* FIFO underflow/overflow flags). When set, this flag will
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* indicate that we have emerged from slot 0.
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/*
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* Reset Audio2 output FIFO's underflow flag (along with any
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* other FIFO underflow/overflow flags). When set, this flag
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* will indicate that we have emerged from slot 0.
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*/
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WR7146(P_ISR, ISR_AFOU);
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writel(ISR_AFOU, devpriv->base_addr + P_ISR);
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/* Wait for the DMA transfer to finish so that there will be data
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* available in the FIFO when time slot 1 tries to transfer a DWORD
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@ -407,7 +403,7 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
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* detection.
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*/
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SETVECT(0, XSD2 | RSD3 | SIB_A2);
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writel(XSD2 | RSD3 | SIB_A2, devpriv->base_addr + VECTPORT(0));
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/* Wait for slot 1 to execute to ensure that the Packet will be
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* transmitted. This is detected by polling the Audio2 output FIFO
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@ -424,7 +420,8 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* stored in the last byte to be shifted out of the FIFO's DWORD
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* buffer register.
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*/
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SETVECT(0, XSD2 | XFIFO_2 | RSD2 | SIB_A2 | EOS);
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writel(XSD2 | XFIFO_2 | RSD2 | SIB_A2 | EOS,
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devpriv->base_addr + VECTPORT(0));
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/* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
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@ -463,7 +460,7 @@ static void SendDAC(struct comedi_device *dev, uint32_t val)
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* In order to do this, we reprogram slot 0 so that it will shift in
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* SD3, which is driven only by a pull-up resistor.
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*/
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SETVECT(0, RSD3 | SIB_A2 | EOS);
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writel(RSD3 | SIB_A2 | EOS, devpriv->base_addr + VECTPORT(0));
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/* Wait for slot 0 to execute, at which time the TSL is setup for
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* the next DAC write. This is detected when FB_BUFFER2 MSB changes
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@ -503,16 +500,16 @@ static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata)
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* disables gating for the DAC clock and all DAC chip selects.
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*/
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/* Choose DAC chip select to be asserted */
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WSImage = (chan & 2) ? WS1 : WS2;
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/* Choose DAC chip select to be asserted. */
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SETVECT(2, XSD2 | XFIFO_1 | WSImage);
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/* Slot 2: Transmit high data byte to target DAC. */
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SETVECT(3, XSD2 | XFIFO_0 | WSImage);
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/* Slot 3: Transmit low data byte to target DAC. */
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SETVECT(4, XSD2 | XFIFO_3 | WS3);
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/* Slot 2: Transmit high data byte to target DAC */
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writel(XSD2 | XFIFO_1 | WSImage, devpriv->base_addr + VECTPORT(2));
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/* Slot 3: Transmit low data byte to target DAC */
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writel(XSD2 | XFIFO_0 | WSImage, devpriv->base_addr + VECTPORT(3));
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/* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
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SETVECT(5, XSD2 | XFIFO_2 | WS3 | EOS);
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/* Slot 5: running after writing target DAC's low data byte. */
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writel(XSD2 | XFIFO_3 | WS3, devpriv->base_addr + VECTPORT(4));
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/* Slot 5: running after writing target DAC's low data byte */
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writel(XSD2 | XFIFO_2 | WS3 | EOS, devpriv->base_addr + VECTPORT(5));
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/* Construct and transmit target DAC's serial packet:
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* ( A10D DDDD ),( DDDD DDDD ),( 0x0F ),( 0x00 ) where A is chan<0>,
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@ -548,14 +545,14 @@ static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan,
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* can be detected.
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*/
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SETVECT(2, XSD2 | XFIFO_1 | WS3);
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/* Slot 2: Send high uint8_t to target TrimDac. */
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SETVECT(3, XSD2 | XFIFO_0 | WS3);
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/* Slot 3: Send low uint8_t to target TrimDac. */
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SETVECT(4, XSD2 | XFIFO_3 | WS1);
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/* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running. */
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SETVECT(5, XSD2 | XFIFO_2 | WS1 | EOS);
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/* Slot 5: Send NOP low uint8_t to DAC0. */
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/* Slot 2: Send high uint8_t to target TrimDac */
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writel(XSD2 | XFIFO_1 | WS3, devpriv->base_addr + VECTPORT(2));
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/* Slot 3: Send low uint8_t to target TrimDac */
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writel(XSD2 | XFIFO_0 | WS3, devpriv->base_addr + VECTPORT(3));
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/* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running */
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writel(XSD2 | XFIFO_3 | WS1, devpriv->base_addr + VECTPORT(4));
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/* Slot 5: Send NOP low uint8_t to DAC0 */
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writel(XSD2 | XFIFO_2 | WS1 | EOS, devpriv->base_addr + VECTPORT(5));
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/* Construct and transmit target DAC's serial packet:
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* ( 0000 AAAA ), ( DDDD DDDD ),( 0x00 ),( 0x00 ) where A<3:0> is the
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@ -949,8 +946,9 @@ static void ResetADC(struct comedi_device *dev, uint8_t *ppl)
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/* Set starting logical address to write RPS commands. */
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pRPS = (uint32_t *) devpriv->RPSBuf.LogicalBase;
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/* Initialize RPS instruction pointer. */
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WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
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/* Initialize RPS instruction pointer */
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writel((uint32_t)devpriv->RPSBuf.PhysicalBase,
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devpriv->base_addr + P_RPSADDR1);
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/* Construct RPS program in RPSBuf DMA buffer */
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@ -1204,13 +1202,13 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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/* Start ADC by pulsing GPIO1 low. */
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GpioImage = RR7146(P_GPIO);
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/* Assert ADC Start command */
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WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
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/* and stretch it out. */
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WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
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WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
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/* Negate ADC Start command. */
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WR7146(P_GPIO, GpioImage | GPIO1_HI);
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/* Assert ADC Start command */
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writel(GpioImage & ~GPIO1_HI, devpriv->base_addr + P_GPIO);
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/* and stretch it out */
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writel(GpioImage & ~GPIO1_HI, devpriv->base_addr + P_GPIO);
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writel(GpioImage & ~GPIO1_HI, devpriv->base_addr + P_GPIO);
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/* Negate ADC Start command */
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writel(GpioImage | GPIO1_HI, devpriv->base_addr + P_GPIO);
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/* Wait for ADC to complete (GPIO2 is asserted high when */
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/* ADC not busy) and for data from previous conversion to */
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@ -1240,12 +1238,12 @@ static int s626_ai_insn_read(struct comedi_device *dev,
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GpioImage = RR7146(P_GPIO);
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/* Assert ADC Start command */
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WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
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/* and stretch it out. */
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WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
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WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
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/* Negate ADC Start command. */
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WR7146(P_GPIO, GpioImage | GPIO1_HI);
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writel(GpioImage & ~GPIO1_HI, devpriv->base_addr + P_GPIO);
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/* and stretch it out */
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writel(GpioImage & ~GPIO1_HI, devpriv->base_addr + P_GPIO);
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writel(GpioImage & ~GPIO1_HI, devpriv->base_addr + P_GPIO);
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/* Negate ADC Start command */
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writel(GpioImage | GPIO1_HI, devpriv->base_addr + P_GPIO);
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/* Wait for the data to arrive in FB BUFFER 1 register. */
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@ -2404,15 +2402,16 @@ static void s626_initialize(struct comedi_device *dev)
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* Set up byte lane steering
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* Intel-compatible local bus (DEBI never times out)
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*/
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WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 |
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(DEBI_TOUT << DEBI_CFG_TOUT_BIT) |
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DEBI_SWAP | DEBI_CFG_INTEL);
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writel(DEBI_CFG_SLAVE16 |
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(DEBI_TOUT << DEBI_CFG_TOUT_BIT) |
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DEBI_SWAP | DEBI_CFG_INTEL,
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devpriv->base_addr + P_DEBICFG);
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/* Disable MMU paging */
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WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE);
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writel(DEBI_PAGE_DISABLE, devpriv->base_addr + P_DEBIPAGE);
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/* Init GPIO so that ADC Start* is negated */
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WR7146(P_GPIO, GPIO_BASE | GPIO1_HI);
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writel(GPIO_BASE | GPIO1_HI, devpriv->base_addr + P_GPIO);
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/* I2C device address for onboard eeprom (revb) */
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devpriv->I2CAdrs = 0xA0;
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@ -2421,7 +2420,7 @@ static void s626_initialize(struct comedi_device *dev)
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* Issue an I2C ABORT command to halt any I2C
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* operation in progress and reset BUSY flag.
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*/
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WR7146(P_I2CSTAT, I2C_CLKSEL | I2C_ABORT);
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writel(I2C_CLKSEL | I2C_ABORT, devpriv->base_addr + P_I2CSTAT);
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s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2);
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while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
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;
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@ -2431,7 +2430,7 @@ static void s626_initialize(struct comedi_device *dev)
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* reg twice to reset all I2C error flags.
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*/
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for (i = 0; i < 2; i++) {
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WR7146(P_I2CSTAT, I2C_CLKSEL);
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writel(I2C_CLKSEL, devpriv->base_addr + P_I2CSTAT);
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s626_mc_enable(dev, MC2_UPLD_IIC, P_MC2);
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while (!s626_mc_test(dev, MC2_UPLD_IIC, P_MC2))
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;
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@ -2443,7 +2442,7 @@ static void s626_initialize(struct comedi_device *dev)
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* DAC data setup times are satisfied, enable DAC serial
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* clock out.
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*/
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WR7146(P_ACON2, ACON2_INIT);
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writel(ACON2_INIT, devpriv->base_addr + P_ACON2);
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/*
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* Set up TSL1 slot list, which is used to control the
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@ -2451,22 +2450,23 @@ static void s626_initialize(struct comedi_device *dev)
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* SIB_A1 = store data uint8_t at next available location
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* in FB BUFFER1 register.
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*/
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WR7146(P_TSL1, RSD1 | SIB_A1);
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WR7146(P_TSL1 + 4, RSD1 | SIB_A1 | EOS);
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writel(RSD1 | SIB_A1, devpriv->base_addr + P_TSL1);
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writel(RSD1 | SIB_A1 | EOS, devpriv->base_addr + P_TSL1 + 4);
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/* Enable TSL1 slot list so that it executes all the time */
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WR7146(P_ACON1, ACON1_ADCSTART);
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writel(ACON1_ADCSTART, devpriv->base_addr + P_ACON1);
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/*
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* Initialize RPS registers used for ADC
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*/
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/* Physical start of RPS program */
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WR7146(P_RPSADDR1, (uint32_t)devpriv->RPSBuf.PhysicalBase);
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writel((uint32_t)devpriv->RPSBuf.PhysicalBase,
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devpriv->base_addr + P_RPSADDR1);
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/* RPS program performs no explicit mem writes */
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WR7146(P_RPSPAGE1, 0);
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writel(0, devpriv->base_addr + P_RPSPAGE1);
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/* Disable RPS timeouts */
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WR7146(P_RPS1_TOUT, 0);
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writel(0, devpriv->base_addr + P_RPS1_TOUT);
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#if 0
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/*
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@ -2522,7 +2522,7 @@ static void s626_initialize(struct comedi_device *dev)
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* burst length = 1 DWORD
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* threshold = 1 DWORD.
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*/
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WR7146(P_PCI_BT_A, 0);
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writel(0, devpriv->base_addr + P_PCI_BT_A);
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/*
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* Init Audio2's output DMA physical addresses. The protection
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@ -2532,8 +2532,9 @@ static void s626_initialize(struct comedi_device *dev)
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*/
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pPhysBuf = devpriv->ANABuf.PhysicalBase +
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(DAC_WDMABUF_OS * sizeof(uint32_t));
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WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf);
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WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t)));
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writel((uint32_t)pPhysBuf, devpriv->base_addr + P_BASEA2_OUT);
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writel((uint32_t)(pPhysBuf + sizeof(uint32_t)),
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devpriv->base_addr + P_PROTA2_OUT);
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/*
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* Cache Audio2's output DMA buffer logical address. This is
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@ -2548,7 +2549,7 @@ static void s626_initialize(struct comedi_device *dev)
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* DMAC will automatically halt and its PCI address pointer
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* will be reset when the protection address is reached.
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*/
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WR7146(P_PAGEA2_OUT, 8);
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writel(8, devpriv->base_addr + P_PAGEA2_OUT);
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/*
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* Initialize time slot list 2 (TSL2), which is used to control
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@ -2563,7 +2564,7 @@ static void s626_initialize(struct comedi_device *dev)
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*/
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/* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2 */
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SETVECT(0, XSD2 | RSD3 | SIB_A2 | EOS);
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writel(XSD2 | RSD3 | SIB_A2 | EOS, devpriv->base_addr + VECTPORT(0));
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|
||||
/*
|
||||
* Initialize slot 1, which is constant. Slot 1 causes a
|
||||
@ -2575,10 +2576,10 @@ static void s626_initialize(struct comedi_device *dev)
|
||||
*/
|
||||
|
||||
/* Slot 1: Fetch DWORD from Audio2's output FIFO */
|
||||
SETVECT(1, LF_A2);
|
||||
writel(LF_A2, devpriv->base_addr + VECTPORT(1));
|
||||
|
||||
/* Start DAC's audio interface (TSL2) running */
|
||||
WR7146(P_ACON1, ACON1_DACSTART);
|
||||
writel(ACON1_DACSTART, devpriv->base_addr + P_ACON1);
|
||||
|
||||
/*
|
||||
* Init Trim DACs to calibrated values. Do it twice because the
|
||||
@ -2761,15 +2762,18 @@ static void s626_detach(struct comedi_device *dev)
|
||||
|
||||
if (devpriv->base_addr) {
|
||||
/* interrupt mask */
|
||||
WR7146(P_IER, 0); /* Disable master interrupt. */
|
||||
WR7146(P_ISR, IRQ_GPIO3 | IRQ_RPS1); /* Clear board's IRQ status flag. */
|
||||
/* Disable master interrupt */
|
||||
writel(0, devpriv->base_addr + P_IER);
|
||||
/* Clear board's IRQ status flag */
|
||||
writel(IRQ_GPIO3 | IRQ_RPS1,
|
||||
devpriv->base_addr + P_ISR);
|
||||
|
||||
/* Disable the watchdog timer and battery charger. */
|
||||
WriteMISC2(dev, 0);
|
||||
|
||||
/* Close all interfaces on 7146 device. */
|
||||
WR7146(P_MC1, MC1_SHUTDOWN);
|
||||
WR7146(P_ACON1, ACON1_BASE);
|
||||
/* Close all interfaces on 7146 device */
|
||||
writel(MC1_SHUTDOWN, devpriv->base_addr + P_MC1);
|
||||
writel(ACON1_BASE, devpriv->base_addr + P_ACON1);
|
||||
|
||||
CloseDMAB(dev, &devpriv->RPSBuf, DMABUF_SIZE);
|
||||
CloseDMAB(dev, &devpriv->ANABuf, DMABUF_SIZE);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user